NEORV32 Software Framework Documentation
The NEORV32 RISC-V Processor
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sw
bootloader
config.h
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// ================================================================================ //
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// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
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// Copyright (c) NEORV32 contributors. //
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// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
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// Licensed under the BSD-3-Clause license, see LICENSE for details. //
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// SPDX-License-Identifier: BSD-3-Clause //
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// ================================================================================ //
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#ifndef CONFIG_H
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#define CONFIG_H
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/**********************************************************************
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* Processor memory layout
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**********************************************************************/
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// Memory base address for the executable
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#ifndef EXE_BASE_ADDR
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#define EXE_BASE_ADDR 0x00000000U
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#endif
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/**********************************************************************
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* UART configuration
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**********************************************************************/
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// Set to 0 to disable UART
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#ifndef UART_EN
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#define UART_EN 1
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#endif
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// UART BAUD rate for serial
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#ifndef UART_BAUD
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#define UART_BAUD 19200
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#endif
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// Set to 1 to enable UART RTS/CTS hardware flow control
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#ifndef UART_HW_HANDSHAKE_EN
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#define UART_HW_HANDSHAKE_EN 0
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#endif
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// Print splash screen
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#ifndef UART_PRINT_SPLASH_EN
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#define UART_PRINT_SPLASH_EN 1
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#endif
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/**********************************************************************
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* Status LED
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**********************************************************************/
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// Set to 0 to disable bootloader status LED at GPIO.gpio_o(STATUS_LED_PIN)
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#ifndef STATUS_LED_EN
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#define STATUS_LED_EN 1
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#endif
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// GPIO output pin for high-active bootloader status LED
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#ifndef STATUS_LED_PIN
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#define STATUS_LED_PIN 0
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#endif
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/**********************************************************************
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* Auto-boot configuration
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**********************************************************************/
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// Enable auto-boot
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#ifndef AUTO_BOOT_EN
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#define AUTO_BOOT_EN 1
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#endif
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// Time until the auto-boot sequence starts (in seconds)
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#ifndef AUTO_BOOT_TIMEOUT
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#define AUTO_BOOT_TIMEOUT 10
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#endif
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/**********************************************************************
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* SPI configuration
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**********************************************************************/
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// Enable SPI (default) including SPI flash boot options
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#ifndef SPI_EN
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#define SPI_EN 1
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#endif
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// SPI flash chip select
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#ifndef SPI_FLASH_CS
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#define SPI_FLASH_CS 0
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#endif
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// SPI flash clock prescaler, see #NEORV32_CLOCK_PRSC_enum
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#ifndef SPI_FLASH_CLK_PRSC
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#define SPI_FLASH_CLK_PRSC CLK_PRSC_64
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#endif
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// SPI flash base address (hast to be aligned to the sector size)
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#ifndef SPI_FLASH_BASE_ADDR
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#define SPI_FLASH_BASE_ADDR 0x00400000U
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#endif
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// SPI flash address bytes (1,2,3,4)
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#ifndef SPI_FLASH_ADDR_BYTES
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#define SPI_FLASH_ADDR_BYTES 3
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#endif
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// SPI flash sector size in bytes
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#ifndef SPI_FLASH_SECTOR_SIZE
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#define SPI_FLASH_SECTOR_SIZE 65536
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#endif
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/**********************************************************************
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* TWI configuration
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**********************************************************************/
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// Enable TWI for copying to RAM
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#ifndef TWI_EN
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#define TWI_EN 0
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#endif
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// TWI clock prescaler, see #NEORV32_CLOCK_PRSC_enum
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#ifndef TWI_CLK_PRSC
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#define TWI_CLK_PRSC CLK_PRSC_1024
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#endif
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// TWI clock divider
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#ifndef TWI_CLK_DIV
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#define TWI_CLK_DIV 3
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#endif
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// TWI allow clock stretching
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#ifndef TWI_CLK_STRECH_EN
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#define TWI_CLK_STRECH_EN 0
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#endif
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// TWI device ID (write address; R/W cleared)
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#ifndef TWI_DEVICE_ID
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#define TWI_DEVICE_ID 0xA0
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#endif
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// TWI flash base address (has to 4-byte aligned)
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#ifndef TWI_FLASH_BASE_ADDR
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#define TWI_FLASH_BASE_ADDR 0x00000000U
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#endif
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// TWI flash address bytes (1,2,3,4)
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#ifndef TWI_FLASH_ADDR_BYTES
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#define TWI_FLASH_ADDR_BYTES 2
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#endif
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// TWI flash bulk write enable
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#ifndef TWI_FLASH_BULK_WRITE_EN
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#define TWI_FLASH_BULK_WRITE_EN 0
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#endif
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#endif
// CONFIG_H
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