NEORV32 - Software Framework Documentation
neorv32_b_extension_intrinsics.h
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1// #################################################################################################
2// # << NEORV32 - Intrinsics + Emulation Functions for the CPU B extension >> #
3// # ********************************************************************************************* #
4// # The intrinsics provided by this library allow to use the hardware bit manipulation unit of #
5// # the RISC-V B CPU extension without the need for support by the compiler. #
6// # ********************************************************************************************* #
7// # BSD 3-Clause License #
8// # #
9// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
10// # #
11// # Redistribution and use in source and binary forms, with or without modification, are #
12// # permitted provided that the following conditions are met: #
13// # #
14// # 1. Redistributions of source code must retain the above copyright notice, this list of #
15// # conditions and the following disclaimer. #
16// # #
17// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
18// # conditions and the following disclaimer in the documentation and/or other materials #
19// # provided with the distribution. #
20// # #
21// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
22// # endorse or promote products derived from this software without specific prior written #
23// # permission. #
24// # #
25// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
26// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
27// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
28// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
29// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
30// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
31// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
32// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
33// # OF THE POSSIBILITY OF SUCH DAMAGE. #
34// # ********************************************************************************************* #
35// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
36// #################################################################################################
37
38
39/**********************************************************************/
48#ifndef neorv32_b_extension_intrinsics_h
49#define neorv32_b_extension_intrinsics_h
50
51
52// ################################################################################################
53// "Intrinsics"
54// ################################################################################################
55
56
57// ================================================================================================
58// Zbb - Base instructions
59// ================================================================================================
60
61/**********************************************************************/
67inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clz(uint32_t rs1) {
68
69 return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00000, rs1, 0b001, 0b0010011);
70}
71
72
73/**********************************************************************/
79inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_ctz(uint32_t rs1) {
80
81 return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00001, rs1, 0b001, 0b0010011);
82}
83
84
85/**********************************************************************/
91inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_cpop(uint32_t rs1) {
92
93 return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00010, rs1, 0b001, 0b0010011);
94}
95
96
97/**********************************************************************/
103inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sextb(uint32_t rs1) {
104
105 return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00100, rs1, 0b001, 0b0010011);
106}
107
108
109/**********************************************************************/
115inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sexth(uint32_t rs1) {
116
117 return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00101, rs1, 0b001, 0b0010011);
118}
119
120
121/**********************************************************************/
127inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_zexth(uint32_t rs1) {
128
129 return CUSTOM_INSTR_R1_TYPE(0b0000100, 0b00000, rs1, 0b100, 0b0110011);
130}
131
132
133/**********************************************************************/
140inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_min(uint32_t rs1, uint32_t rs2) {
141
142 return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b100, 0b0110011);
143}
144
145
146/**********************************************************************/
153inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_minu(uint32_t rs1, uint32_t rs2) {
154
155 return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b101, 0b0110011);
156}
157
158
159/**********************************************************************/
166inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_max(uint32_t rs1, uint32_t rs2) {
167
168 return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b110, 0b0110011);
169}
170
171
172/**********************************************************************/
179inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_maxu(uint32_t rs1, uint32_t rs2) {
180
181 return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b111, 0b0110011);
182}
183
184
185/**********************************************************************/
192inline inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_andn(uint32_t rs1, uint32_t rs2) {
193
194 return CUSTOM_INSTR_R2_TYPE(0b0100000, rs2, rs1, 0b111, 0b0110011);
195}
196
197
198/**********************************************************************/
205inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_orn(uint32_t rs1, uint32_t rs2) {
206
207 return CUSTOM_INSTR_R2_TYPE(0b0100000, rs2, rs1, 0b110, 0b0110011);
208}
209
210
211/**********************************************************************/
218inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_xnor(uint32_t rs1, uint32_t rs2) {
219
220 return CUSTOM_INSTR_R2_TYPE(0b0100000, rs2, rs1, 0b100, 0b0110011);
221}
222
223
224/**********************************************************************/
231inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rol(uint32_t rs1, uint32_t rs2) {
232
233 return CUSTOM_INSTR_R2_TYPE(0b0110000, rs2, rs1, 0b001, 0b0110011);
234}
235
236
237/**********************************************************************/
244inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_ror(uint32_t rs1, uint32_t rs2) {
245
246 return CUSTOM_INSTR_R2_TYPE(0b0110000, rs2, rs1, 0b101, 0b0110011);
247}
248
249
250/**********************************************************************/
257inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rori20(uint32_t rs1) {
258
259 return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b10100, rs1, 0b101, 0b0010011);
260}
261
262
263/**********************************************************************/
269inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_orcb(uint32_t rs1) {
270
271 return CUSTOM_INSTR_R1_TYPE(0b0010100, 0b00111, rs1, 0b101, 0b0010011);
272}
273
274
275/**********************************************************************/
281inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rev8(uint32_t rs1) {
282
283 return CUSTOM_INSTR_R1_TYPE(0b0110100, 0b11000, rs1, 0b101, 0b0010011);
284}
285
286
287// ================================================================================================
288// Zba - Address-generation instructions
289// ================================================================================================
290
291/**********************************************************************/
298inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh1add(uint32_t rs1, uint32_t rs2) {
299
300 return CUSTOM_INSTR_R2_TYPE(0b0010000, rs2, rs1, 0b010, 0b0110011);
301}
302
303
304/**********************************************************************/
311inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh2add(uint32_t rs1, uint32_t rs2) {
312
313 return CUSTOM_INSTR_R2_TYPE(0b0010000, rs2, rs1, 0b100, 0b0110011);
314}
315
316/**********************************************************************/
323inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh3add(uint32_t rs1, uint32_t rs2) {
324
325 return CUSTOM_INSTR_R2_TYPE(0b0010000, rs2, rs1, 0b110, 0b0110011);
326}
327
328
329// ================================================================================================
330// Zbs - Single-bit instructions
331// ================================================================================================
332
333
334/**********************************************************************/
341inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bclr(uint32_t rs1, uint32_t rs2) {
342
343 return CUSTOM_INSTR_R2_TYPE(0b0100100, rs2, rs1, 0b001, 0b0110011);
344}
345
346
347/**********************************************************************/
354inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bclri20(uint32_t rs1) {
355
356 return CUSTOM_INSTR_R1_TYPE(0b0100100, 0b10100, rs1, 0b001, 0b0010011);
357}
358
359
360/**********************************************************************/
367inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bext(uint32_t rs1, uint32_t rs2) {
368
369 return CUSTOM_INSTR_R2_TYPE(0b0100100, rs2, rs1, 0b101, 0b0110011);
370}
371
372
373/**********************************************************************/
380inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bexti20(uint32_t rs1) {
381
382 return CUSTOM_INSTR_R1_TYPE(0b0100100, 0b10100, rs1, 0b101, 0b0010011);
383}
384
385
386/**********************************************************************/
393inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_binv(uint32_t rs1, uint32_t rs2) {
394
395 return CUSTOM_INSTR_R2_TYPE(0b0110100, rs2, rs1, 0b001, 0b0110011);
396}
397
398
399/**********************************************************************/
406inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_binvi20(uint32_t rs1) {
407
408 return CUSTOM_INSTR_R1_TYPE(0b0110100, 0b10100, rs1, 0b001, 0b0010011);
409}
410
411
412/**********************************************************************/
419inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bset(uint32_t rs1, uint32_t rs2) {
420
421 return CUSTOM_INSTR_R2_TYPE(0b0010100, rs2, rs1, 0b001, 0b0110011);
422}
423
424
425/**********************************************************************/
432inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bseti20(uint32_t rs1) {
433
434 return CUSTOM_INSTR_R1_TYPE(0b0010100, 0b10100, rs1, 0b001, 0b0010011);
435}
436
437
438// ================================================================================================
439// Zbc - Carry-less multiplication instructions
440// ================================================================================================
441
442
443/**********************************************************************/
450inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clmul(uint32_t rs1, uint32_t rs2) {
451
452 return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b001, 0b0110011);
453}
454
455
456/**********************************************************************/
463inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clmulh(uint32_t rs1, uint32_t rs2) {
464
465 return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b011, 0b0110011);
466}
467
468
469/**********************************************************************/
476inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clmulr(uint32_t rs1, uint32_t rs2) {
477
478 return CUSTOM_INSTR_R2_TYPE(0b0000101, rs1, rs2, 0b010, 0b0110011);
479}
480
481
482// ################################################################################################
483// Emulation functions
484// ################################################################################################
485
486
487// ================================================================================================
488// Zbb - Base instructions
489// ================================================================================================
490
491
492/**********************************************************************/
498uint32_t riscv_emulate_clz(uint32_t rs1) {
499
500 uint32_t sreg = rs1;
501 uint32_t cnt = 0;
502
503 while(1) {
504 if (sreg & 0x80000000UL) {
505 break;
506 }
507 else {
508 sreg <<= 1;
509 cnt++;
510 }
511 }
512
513 return cnt;
514}
515
516
517/**********************************************************************/
523uint32_t riscv_emulate_ctz(uint32_t rs1) {
524
525 uint32_t sreg = rs1;
526 uint32_t cnt = 0;
527
528 while(1) {
529 if (sreg & 1) {
530 break;
531 }
532 else {
533 sreg >>= 1;
534 cnt++;
535 }
536 }
537
538 return cnt;
539}
540
541
542/**********************************************************************/
548uint32_t riscv_emulate_cpop(uint32_t rs1) {
549
550 uint32_t sreg = rs1;
551 uint32_t cnt = 0;
552 int i;
553
554 for (i=0; i<32; i++) {
555 if (sreg & 1) {
556 cnt++;
557 }
558 sreg >>= 1;
559 }
560
561 return cnt;
562}
563
564
565/**********************************************************************/
571uint32_t riscv_emulate_sextb(uint32_t rs1) {
572
573 uint32_t tmp = rs1 & 0xff;
574
575 if (tmp & 0x80) {
576 tmp |= 0xFFFFFF00UL;
577 }
578
579 return tmp;
580}
581
582
583/**********************************************************************/
589uint32_t riscv_emulate_sexth(uint32_t rs1) {
590
591 uint32_t tmp = rs1 & 0xffff;
592
593 if (tmp & 0x8000) {
594 tmp |= 0xFFFF0000UL;
595 }
596
597 return tmp;
598}
599
600
601/**********************************************************************/
607uint32_t riscv_emulate_zexth(uint32_t rs1) {
608
609 return rs1 & 0x0000FFFFUL;
610}
611
612
613/**********************************************************************/
620uint32_t riscv_emulate_min(uint32_t rs1, uint32_t rs2) {
621
622 int32_t s_opa = (int32_t)rs1;
623 int32_t s_opb = (int32_t)rs2;
624
625 if (s_opa < s_opb) {
626 return rs1;
627 }
628 else {
629 return rs2;
630 }
631}
632
633
634/**********************************************************************/
641uint32_t riscv_emulate_minu(uint32_t rs1, uint32_t rs2) {
642
643 if (rs1 < rs2) {
644 return rs1;
645 }
646 else {
647 return rs2;
648 }
649}
650
651
652/**********************************************************************/
659uint32_t riscv_emulate_max(uint32_t rs1, uint32_t rs2) {
660
661 int32_t s_opa = (int32_t)rs1;
662 int32_t s_opb = (int32_t)rs2;
663
664 if (s_opa < s_opb) {
665 return rs2;
666 }
667 else {
668 return rs1;
669 }
670}
671
672
673/**********************************************************************/
680uint32_t riscv_emulate_maxu(uint32_t rs1, uint32_t rs2) {
681
682 if (rs1 < rs2) {
683 return rs2;
684 }
685 else {
686 return rs1;
687 }
688}
689
690
691/**********************************************************************/
698uint32_t riscv_emulate_andn(uint32_t rs1, uint32_t rs2) {
699
700 return rs1 & (~rs2);
701}
702
703
704/**********************************************************************/
711uint32_t riscv_emulate_orn(uint32_t rs1, uint32_t rs2) {
712
713 return rs1 | (~rs2);
714}
715
716
717/**********************************************************************/
724uint32_t riscv_emulate_xnor(uint32_t rs1, uint32_t rs2) {
725
726 return rs1 ^ (~rs2);
727}
728
729
730/**********************************************************************/
737uint32_t riscv_emulate_rol(uint32_t rs1, uint32_t rs2) {
738
739 uint32_t shamt = rs2 & 0x1f;
740
741 uint32_t tmp_a = rs1 << shamt;
742 uint32_t tmp_b = rs1 >> (32-shamt);
743
744 return tmp_a | tmp_b;
745}
746
747
748/**********************************************************************/
755uint32_t riscv_emulate_ror(uint32_t rs1, uint32_t rs2) {
756
757 uint32_t shamt = rs2 & 0x1f;
758
759 uint32_t tmp_a = rs1 >> shamt;
760 uint32_t tmp_b = rs1 << (32-shamt);
761
762 return tmp_a | tmp_b;
763}
764
765
766/**********************************************************************/
772uint32_t riscv_emulate_rev8(uint32_t rs1) {
773
774 uint32_t tmp_a = (rs1 & 0x000000ffUL) << 24;
775 uint32_t tmp_b = (rs1 & 0x0000ff00UL) << 8;
776 uint32_t tmp_c = (rs1 & 0x00ff0000UL) >> 8;
777 uint32_t tmp_d = (rs1 & 0xff000000UL) >> 24;
778
779 return tmp_a | tmp_b | tmp_c | tmp_d;
780}
781
782
783/**********************************************************************/
789uint32_t riscv_emulate_orcb(uint32_t rs1) {
790
791 uint32_t tmp = 0;
792
793 if (rs1 & 0x000000ffUL) {
794 tmp |= 0x000000ffUL;
795 }
796 if (rs1 & 0x0000ff00UL) {
797 tmp |= 0x0000ff00UL;
798 }
799 if (rs1 & 0x00ff0000UL) {
800 tmp |= 0x00ff0000UL;
801 }
802 if (rs1 & 0xff000000UL) {
803 tmp |= 0xff000000UL;
804 }
805
806 return tmp;
807}
808
809
810// ================================================================================================
811// Zba - Address generation instructions
812// ================================================================================================
813
814
815/**********************************************************************/
822uint32_t riscv_emulate_sh1add(uint32_t rs1, uint32_t rs2) {
823
824 return rs2 + (rs1 << 1);
825}
826
827
828/**********************************************************************/
835uint32_t riscv_emulate_sh2add(uint32_t rs1, uint32_t rs2) {
836
837 return rs2 + (rs1 << 2);
838}
839
840
841/**********************************************************************/
848uint32_t riscv_emulate_sh3add(uint32_t rs1, uint32_t rs2) {
849
850 return rs2 + (rs1 << 3);
851}
852
853
854// ================================================================================================
855// Zbs - Single-bit instructions
856// ================================================================================================
857
858
859/**********************************************************************/
866uint32_t riscv_emulate_bclr(uint32_t rs1, uint32_t rs2) {
867
868 uint32_t shamt = rs2 & 0x1f;
869 uint32_t tmp = 1 << shamt;
870
871 return rs1 & (~tmp);
872}
873
874
875/**********************************************************************/
882uint32_t riscv_emulate_bext(uint32_t rs1, uint32_t rs2) {
883
884 uint32_t shamt = rs2 & 0x1f;
885 uint32_t tmp = rs1 >> shamt;
886
887 return tmp & 1;
888}
889
890
891/**********************************************************************/
898uint32_t riscv_emulate_binv(uint32_t rs1, uint32_t rs2) {
899
900 uint32_t shamt = rs2 & 0x1f;
901 uint32_t tmp = 1 << shamt;
902
903 return rs1 ^ tmp;
904}
905
906
907/**********************************************************************/
914uint32_t riscv_emulate_bset(uint32_t rs1, uint32_t rs2) {
915
916 uint32_t shamt = rs2 & 0x1f;
917 uint32_t tmp = 1 << shamt;
918
919 return rs1 | tmp;
920}
921
922
923// ================================================================================================
924// Zbc - Carry-less multiplication instructions
925// ================================================================================================
926
927
928/**********************************************************************/
935uint32_t riscv_emulate_clmul(uint32_t rs1, uint32_t rs2) {
936
937 uint32_t i;
938 uint64_t tmp;
939 union {
940 uint64_t uint64;
941 uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
942 } res;
943
944 res.uint64 = 0;
945 for (i=0; i<32; i++) {
946 if ((rs2 >> i) & 1) {
947 tmp = (uint64_t)rs1;
948 tmp = tmp << i;
949 res.uint64 = res.uint64 ^ tmp;
950 }
951 }
952
953 return res.uint32[0];
954}
955
956
957/**********************************************************************/
964uint32_t riscv_emulate_clmulh(uint32_t rs1, uint32_t rs2) {
965
966 uint32_t i;
967 uint64_t tmp;
968 union {
969 uint64_t uint64;
970 uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
971 } res;
972
973 res.uint64 = 0;
974 for (i=0; i<32; i++) {
975 if ((rs2 >> i) & 1) {
976 tmp = (uint64_t)rs1;
977 tmp = tmp << i;
978 res.uint64 = res.uint64 ^ tmp;
979 }
980 }
981
982 return res.uint32[1];
983}
984
985
986/**********************************************************************/
993uint32_t riscv_emulate_clmulr(uint32_t rs1, uint32_t rs2) {
994
995 uint32_t i;
996 uint64_t tmp;
997 union {
998 uint64_t uint64;
999 uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
1000 } res;
1001
1002 // bit-reversal of input operands
1003 uint32_t rs1_rev = 0, rs2_rev = 0;
1004 for (i=0; i<32; i++) {
1005 rs1_rev <<= 1;
1006 if ((rs1 >> i) & 1) {
1007 rs1_rev |= 1;
1008 }
1009 rs2_rev <<= 1;
1010 if ((rs2 >> i) & 1) {
1011 rs2_rev |= 1;
1012 }
1013 }
1014
1015 res.uint64 = 0;
1016 for (i=0; i<32; i++) {
1017 if ((rs2_rev >> i) & 1) {
1018 tmp = (uint64_t)rs1_rev;
1019 tmp = tmp << i;
1020 res.uint64 = res.uint64 ^ tmp;
1021 }
1022 }
1023
1024 // bit-reversal of result
1025 uint32_t result = 0;
1026 for (i=0; i<32; i++) {
1027 result <<= 1;
1028 if ((res.uint32[0] >> i) & 1) {
1029 result |= 1;
1030 }
1031 }
1032
1033 return result;
1034}
1035
1036
1037#endif // neorv32_b_extension_intrinsics_h
uint32_t riscv_emulate_rev8(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:772
uint32_t riscv_intrinsic_clz(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:67
uint32_t riscv_intrinsic_sextb(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:103
uint32_t riscv_intrinsic_clmul(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:450
uint32_t riscv_emulate_sh1add(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:822
uint32_t riscv_emulate_xnor(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:724
uint32_t riscv_emulate_clmul(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:935
uint32_t riscv_intrinsic_bset(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:419
uint32_t riscv_emulate_sh2add(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:835
uint32_t riscv_emulate_orn(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:711
uint32_t riscv_emulate_bset(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:914
uint32_t riscv_intrinsic_rev8(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:281
uint32_t riscv_intrinsic_ror(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:244
uint32_t riscv_emulate_orcb(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:789
uint32_t riscv_intrinsic_sh3add(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:323
uint32_t riscv_emulate_bclr(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:866
uint32_t riscv_emulate_clmulh(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:964
uint32_t riscv_emulate_sextb(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:571
uint32_t riscv_emulate_ror(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:755
uint32_t riscv_emulate_sexth(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:589
uint32_t riscv_intrinsic_orn(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:205
uint32_t riscv_intrinsic_rori20(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:257
uint32_t riscv_intrinsic_rol(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:231
uint32_t riscv_intrinsic_sh1add(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:298
uint32_t riscv_emulate_maxu(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:680
uint32_t riscv_emulate_clmulr(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:993
uint32_t riscv_intrinsic_binv(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:393
uint32_t riscv_emulate_andn(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:698
uint32_t riscv_intrinsic_orcb(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:269
uint32_t riscv_emulate_max(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:659
uint32_t riscv_emulate_binv(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:898
uint32_t riscv_emulate_minu(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:641
uint32_t riscv_emulate_clz(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:498
uint32_t riscv_intrinsic_max(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:166
uint32_t riscv_intrinsic_bclr(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:341
uint32_t riscv_intrinsic_bexti20(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:380
uint32_t riscv_intrinsic_andn(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:192
uint32_t riscv_intrinsic_sh2add(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:311
uint32_t riscv_emulate_sh3add(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:848
uint32_t riscv_emulate_zexth(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:607
uint32_t riscv_intrinsic_binvi20(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:406
uint32_t riscv_intrinsic_bclri20(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:354
uint32_t riscv_intrinsic_clmulr(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:476
uint32_t riscv_emulate_cpop(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:548
uint32_t riscv_intrinsic_clmulh(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:463
uint32_t riscv_emulate_min(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:620
uint32_t riscv_emulate_ctz(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:523
uint32_t riscv_emulate_bext(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:882
uint32_t riscv_intrinsic_ctz(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:79
uint32_t riscv_intrinsic_cpop(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:91
uint32_t riscv_intrinsic_xnor(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:218
uint32_t riscv_emulate_rol(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:737
uint32_t riscv_intrinsic_sexth(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:115
uint32_t riscv_intrinsic_min(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:140
uint32_t riscv_intrinsic_bext(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:367
uint32_t riscv_intrinsic_zexth(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:127
uint32_t riscv_intrinsic_minu(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:153
uint32_t riscv_intrinsic_bseti20(uint32_t rs1)
Definition: neorv32_b_extension_intrinsics.h:432
uint32_t riscv_intrinsic_maxu(uint32_t rs1, uint32_t rs2)
Definition: neorv32_b_extension_intrinsics.h:179