neorv32_onewire.h

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// ================================================================================ //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
// Copyright (c) NEORV32 contributors.                                              //
// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  //
// Licensed under the BSD-3-Clause license, see LICENSE for details.                //
// SPDX-License-Identifier: BSD-3-Clause                                            //
// ================================================================================ //

 
#ifndef NEORV32_ONEWIRE_H
#define NEORV32_ONEWIRE_H
 
#include <stdint.h>
 
 
/**********************************************************************/
typedef volatile struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL; 
  uint32_t DCMD; 
} neorv32_onewire_t;

#define NEORV32_ONEWIRE ((neorv32_onewire_t*) (NEORV32_ONEWIRE_BASE))

enum NEORV32_ONEWIRE_CTRL_enum {
  ONEWIRE_CTRL_EN        =  0, 
  ONEWIRE_CTRL_CLEAR     =  1, 
  ONEWIRE_CTRL_PRSC0     =  2, 
  ONEWIRE_CTRL_PRSC1     =  3, 
  ONEWIRE_CTRL_CLKDIV0   =  4, 
  ONEWIRE_CTRL_CLKDIV7   = 11, 
 
  ONEWIRE_CTRL_FIFO_LSB  = 15, 
  ONEWIRE_CTRL_FIFO_MSB  = 18, 
 
  ONEWIRE_CTRL_TX_FULL   = 28, 
  ONEWIRE_CTRL_RX_AVAIL  = 29, 
  ONEWIRE_CTRL_SENSE     = 30, 
  ONEWIRE_CTRL_BUSY      = 31, 
};

enum NEORV32_ONEWIRE_DCMD_enum {
  ONEWIRE_DCMD_DATA_LSB = 0,  
  ONEWIRE_DCMD_DATA_MSB = 7,  
  ONEWIRE_DCMD_CMD_LO   = 8,  
  ONEWIRE_DCMD_CMD_HI   = 9,  
  ONEWIRE_DCMD_PRESENCE = 10  
};

 
 
/**********************************************************************/
#define ONEWIRE_CMD_NOP   (0b00) // no operation
#define ONEWIRE_CMD_BIT   (0b01) // read/write single bit
#define ONEWIRE_CMD_BYTE  (0b10) // read/write full byte
#define ONEWIRE_CMD_RESET (0b11) // generate reset pulse and check for presence
 
 
/**********************************************************************/
int     neorv32_onewire_available(void);
int     neorv32_onewire_get_fifo_depth(void);
int     neorv32_onewire_setup(uint32_t t_base);
void    neorv32_onewire_enable(void);
void    neorv32_onewire_disable(void);
void    neorv32_onewire_flush(void);
int     neorv32_onewire_sense(void);
 
int     neorv32_onewire_busy(void);
void    neorv32_onewire_reset(void);
int     neorv32_onewire_reset_get_presence(void);
void    neorv32_onewire_read_bit(void);
uint8_t neorv32_onewire_read_bit_get(void);
void    neorv32_onewire_write_bit(uint8_t bit);
void    neorv32_onewire_read_byte(void);
uint8_t neorv32_onewire_read_byte_get(void);
void    neorv32_onewire_write_byte(uint8_t byte);
 
int     neorv32_onewire_reset_blocking(void);
uint8_t neorv32_onewire_read_bit_blocking(void);
void    neorv32_onewire_write_bit_blocking(uint8_t bit);
uint8_t neorv32_onewire_read_byte_blocking(void);
void    neorv32_onewire_write_byte_blocking(uint8_t byte);
 
 
#endif // NEORV32_ONEWIRE_H