neorv32_semihosting.h

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// ================================================================================ //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
// Copyright (c) NEORV32 contributors.                                              //
// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  //
// Licensed under the BSD-3-Clause license, see LICENSE for details.                //
// SPDX-License-Identifier: BSD-3-Clause                                            //
// ================================================================================ //

 
#ifndef NEORV32_SEMIHOSTING_H
#define NEORV32_SEMIHOSTING_H
 
#include <stdint.h>
 
 
/**********************************************************************/
enum SEMIHOSTING_SYS_enum {
  SEMIHOSTING_SYS_OPEN        = 0x01, 
  SEMIHOSTING_SYS_CLOSE       = 0x02, 
  SEMIHOSTING_SYS_WRITEC      = 0x03, 
  SEMIHOSTING_SYS_WRITE0      = 0x04, 
  SEMIHOSTING_SYS_WRITE       = 0x05, 
  SEMIHOSTING_SYS_READ        = 0x06, 
  SEMIHOSTING_SYS_READC       = 0x07, 
  SEMIHOSTING_SYS_ISTTY       = 0x09, 
  SEMIHOSTING_SYS_SEEK        = 0x0A, 
  SEMIHOSTING_SYS_FLEN        = 0x0C, 
  SEMIHOSTING_SYS_TMPNAME     = 0x0D, 
  SEMIHOSTING_SYS_REMOVE      = 0x0E, 
  SEMIHOSTING_SYS_RENAME      = 0x0F, 
  SEMIHOSTING_SYS_CLOCK       = 0x10, 
  SEMIHOSTING_SYS_TIME        = 0x11, 
  SEMIHOSTING_SYS_SYSTEM      = 0x12, 
  SEMIHOSTING_SYS_ERRNO       = 0x13, 
  SEMIHOSTING_SYS_GET_CMDLINE = 0x15, 
  SEMIHOSTING_SYS_HEAPINFO    = 0x16, 
  SEMIHOSTING_SYS_EXCEPTION   = 0x18, 
  SEMIHOSTING_SYS_ELLAPSED    = 0x30, 
  SEMIHOSTING_SYS_TICKFREQ    = 0x31  
};

 
 
/**********************************************************************/
enum SEMIHOST_OPEN_MODE_enum {
  SEMIHOSTING_OPEN_R       = 0,
  SEMIHOSTING_OPEN_RB      = 1,
  SEMIHOSTING_OPEN_R_PLUS  = 2,
  SEMIHOSTING_OPEN_RB_PLUS = 3,
  SEMIHOSTING_OPEN_W       = 4,
  SEMIHOSTING_OPEN_WB      = 5,
  SEMIHOSTING_OPEN_W_PLUS  = 6,
  SEMIHOSTING_OPEN_WB_PLUS = 7,
  SEMIHOSTING_OPEN_A       = 8,
  SEMIHOSTING_OPEN_AB      = 9,
  SEMIHOSTING_OPEN_A_PLUS  = 10,
  SEMIHOSTING_OPEN_AB_PLUS = 11
};
 
 
/**********************************************************************/
void neorv32_semihosting_putc(char c);
void neorv32_semihosting_puts(const char* pnt);
char neorv32_semihosting_getc(void);
//
int neorv32_semihosting_open(char *path, int mode);
int neorv32_semihosting_close(int file);
int neorv32_semihosting_write(int file, char *buffer, int len);
int neorv32_semihosting_read(int file, char *buffer, int len);
int neorv32_semihosting_istty(int file);
int neorv32_semihosting_seek(int file, int pos);
int neorv32_semihosting_flen(int file);
int neorv32_semihosting_time(void);
int neorv32_semihosting_system(char *cmd);
 
 
/**********************************************************************/
inline int __attribute__ ((always_inline)) neorv32_semihosting_req(int id, void* arg) {
 
  register int value asm ("a0") = id;
  register void* data asm ("a1") = arg;
  asm volatile (
    " .option push      \n"
    " .option norvc     \n" // we need 32-bit instruction words here
    " .align 4          \n" // this has to be aligned
    " slli x0, x0, 0x1f \n" // magic triplet: entry NOP
    " ebreak            \n" // magic triplet: break to debugger
    " srai x0, x0, 0x07 \n" // magic triplet: exit NOP
    " .option pop       \n"
    : "=r" (value) : "0" (value), "r" (data) : "memory"
  );
  return value;
}
 
 
#endif // NEORV32_SEMIHOSTING_H