neorv32_sysinfo.h

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// ================================================================================ //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
// Copyright (c) NEORV32 contributors.                                              //
// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  //
// Licensed under the BSD-3-Clause license, see LICENSE for details.                //
// SPDX-License-Identifier: BSD-3-Clause                                            //
// ================================================================================ //
 
#ifndef neorv32_sysinfo_h
#define neorv32_sysinfo_h
 
#include <stdint.h>
 
 
/**********************************************************************/
typedef volatile struct __attribute__((packed,aligned(4))) {
        uint32_t CLK;    
  const uint8_t  MEM[4]; 
  const uint32_t SOC;    
  const uint32_t CACHE;  
} neorv32_sysinfo_t;
 
#define NEORV32_SYSINFO ((neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE))
 
enum NEORV32_SYSINFO_MEM_enum {
  SYSINFO_MEM_IMEM = 0, 
  SYSINFO_MEM_DMEM = 1, 
  SYSINFO_MEM_res  = 2, 
  SYSINFO_MEM_BOOT = 3  
};
 
enum NEORV32_SYSINFO_SOC_enum {
  SYSINFO_SOC_BOOTLOADER   =  0, 
  SYSINFO_SOC_XBUS         =  1, 
  SYSINFO_SOC_MEM_INT_IMEM =  2, 
  SYSINFO_SOC_MEM_INT_DMEM =  3, 
  SYSINFO_SOC_OCD          =  4, 
  SYSINFO_SOC_ICACHE       =  5, 
  SYSINFO_SOC_DCACHE       =  6, 
  SYSINFO_SOC_CLOCK_GATING =  7, 
  SYSINFO_SOC_XBUS_CACHE   =  8, 
  SYSINFO_SOC_XIP          =  9, 
  SYSINFO_SOC_XIP_CACHE    = 10, 
  SYSINFO_SOC_OCD_AUTH     = 11, 
  SYSINFO_SOC_IMEM_ROM     = 12, 
  SYSINFO_SOC_IO_DMA       = 14, 
  SYSINFO_SOC_IO_GPIO      = 15, 
  SYSINFO_SOC_IO_MTIME     = 16, 
  SYSINFO_SOC_IO_UART0     = 17, 
  SYSINFO_SOC_IO_SPI       = 18, 
  SYSINFO_SOC_IO_TWI       = 19, 
  SYSINFO_SOC_IO_PWM       = 20, 
  SYSINFO_SOC_IO_WDT       = 21, 
  SYSINFO_SOC_IO_CFS       = 22, 
  SYSINFO_SOC_IO_TRNG      = 23, 
  SYSINFO_SOC_IO_SDI       = 24, 
  SYSINFO_SOC_IO_UART1     = 25, 
  SYSINFO_SOC_IO_NEOLED    = 26, 
  SYSINFO_SOC_IO_XIRQ      = 27, 
  SYSINFO_SOC_IO_GPTMR     = 28, 
  SYSINFO_SOC_IO_SLINK     = 29, 
  SYSINFO_SOC_IO_ONEWIRE   = 30, 
  SYSINFO_SOC_IO_CRC       = 31  
};
 
 enum NEORV32_SYSINFO_CACHE_enum {
  SYSINFO_CACHE_INST_BLOCK_SIZE_0 =  0, 
  SYSINFO_CACHE_INST_BLOCK_SIZE_3 =  3, 
  SYSINFO_CACHE_INST_NUM_BLOCKS_0 =  4, 
  SYSINFO_CACHE_INST_NUM_BLOCKS_3 =  7, 
  SYSINFO_CACHE_DATA_BLOCK_SIZE_0 =  8, 
  SYSINFO_CACHE_DATA_BLOCK_SIZE_3 = 11, 
  SYSINFO_CACHE_DATA_NUM_BLOCKS_0 = 12, 
  SYSINFO_CACHE_DATA_NUM_BLOCKS_3 = 15, 
  SYSINFO_CACHE_XIP_BLOCK_SIZE_0  = 16, 
  SYSINFO_CACHE_XIP_BLOCK_SIZE_3  = 19, 
  SYSINFO_CACHE_XIP_NUM_BLOCKS_0  = 20, 
  SYSINFO_CACHE_XIP_NUM_BLOCKS_3  = 23, 
  SYSINFO_CACHE_XBUS_BLOCK_SIZE_0 = 24, 
  SYSINFO_CACHE_XBUS_BLOCK_SIZE_3 = 27, 
  SYSINFO_CACHE_XBUS_NUM_BLOCKS_0 = 28, 
  SYSINFO_CACHE_XBUS_NUM_BLOCKS_3 = 31  
};
/**********************************************************************/
uint32_t neorv32_sysinfo_get_clk(void);
void     neorv32_sysinfo_set_clk(uint32_t clock);
#endif // neorv32_sysinfo_h