NEORV32 Software Framework Documentation
The NEORV32 RISC-V Processor
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Here is a list of all documented enum values with links to the documentation:
- h -
HPMCNT_EVENT_BRANCH :
neorv32_cpu_csr.h
HPMCNT_EVENT_BRANCHED :
neorv32_cpu_csr.h
HPMCNT_EVENT_COMPR :
neorv32_cpu_csr.h
HPMCNT_EVENT_CY :
neorv32_cpu_csr.h
HPMCNT_EVENT_IR :
neorv32_cpu_csr.h
HPMCNT_EVENT_LOAD :
neorv32_cpu_csr.h
HPMCNT_EVENT_STORE :
neorv32_cpu_csr.h
HPMCNT_EVENT_TM :
neorv32_cpu_csr.h
HPMCNT_EVENT_TRAP :
neorv32_cpu_csr.h
HPMCNT_EVENT_WAIT_ALU :
neorv32_cpu_csr.h
HPMCNT_EVENT_WAIT_DIS :
neorv32_cpu_csr.h
HPMCNT_EVENT_WAIT_LSU :
neorv32_cpu_csr.h
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