neorv32_cpu_csr.h File Reference

Control and Status Registers (CSR) definitions. More...

Go to the source code of this file.

Enumerations
enum	NEORV32_CSR_enum {   CSR_FFLAGS = 0x001 , CSR_FRM = 0x002 , CSR_FCSR = 0x003 , CSR_MSTATUS = 0x300 ,   CSR_MISA = 0x301 , CSR_MIE = 0x304 , CSR_MTVEC = 0x305 , CSR_MCOUNTEREN = 0x306 ,   CSR_MENVCFG = 0x30a , CSR_MSTATUSH = 0x310 , CSR_MENVCFGH = 0x31a , CSR_MCOUNTINHIBIT = 0x320 ,   CSR_MHPMEVENT3 = 0x323 , CSR_MHPMEVENT4 = 0x324 , CSR_MHPMEVENT5 = 0x325 , CSR_MHPMEVENT6 = 0x326 ,   CSR_MHPMEVENT7 = 0x327 , CSR_MHPMEVENT8 = 0x328 , CSR_MHPMEVENT9 = 0x329 , CSR_MHPMEVENT10 = 0x32a ,   CSR_MHPMEVENT11 = 0x32b , CSR_MHPMEVENT12 = 0x32c , CSR_MHPMEVENT13 = 0x32d , CSR_MHPMEVENT14 = 0x32e ,   CSR_MHPMEVENT15 = 0x32f , CSR_MHPMEVENT16 = 0x330 , CSR_MHPMEVENT17 = 0x331 , CSR_MHPMEVENT18 = 0x332 ,   CSR_MHPMEVENT19 = 0x333 , CSR_MHPMEVENT20 = 0x334 , CSR_MHPMEVENT21 = 0x335 , CSR_MHPMEVENT22 = 0x336 ,   CSR_MHPMEVENT23 = 0x337 , CSR_MHPMEVENT24 = 0x338 , CSR_MHPMEVENT25 = 0x339 , CSR_MHPMEVENT26 = 0x33a ,   CSR_MHPMEVENT27 = 0x33b , CSR_MHPMEVENT28 = 0x33c , CSR_MHPMEVENT29 = 0x33d , CSR_MHPMEVENT30 = 0x33e ,   CSR_MHPMEVENT31 = 0x33f , CSR_MSCRATCH = 0x340 , CSR_MEPC = 0x341 , CSR_MCAUSE = 0x342 ,   CSR_MTVAL = 0x343 , CSR_MIP = 0x344 , CSR_PMPCFG0 = 0x3a0 , CSR_PMPCFG1 = 0x3a1 ,   CSR_PMPCFG2 = 0x3a2 , CSR_PMPCFG3 = 0x3a3 , CSR_PMPADDR0 = 0x3b0 , CSR_PMPADDR1 = 0x3b1 ,   CSR_PMPADDR2 = 0x3b2 , CSR_PMPADDR3 = 0x3b3 , CSR_PMPADDR4 = 0x3b4 , CSR_PMPADDR5 = 0x3b5 ,   CSR_PMPADDR6 = 0x3b6 , CSR_PMPADDR7 = 0x3b7 , CSR_PMPADDR8 = 0x3b8 , CSR_PMPADDR9 = 0x3b9 ,   CSR_PMPADDR10 = 0x3ba , CSR_PMPADDR11 = 0x3bb , CSR_PMPADDR12 = 0x3bc , CSR_PMPADDR13 = 0x3bd ,   CSR_PMPADDR14 = 0x3be , CSR_PMPADDR15 = 0x3bf , CSR_TSELECT = 0x7a0 , CSR_TDATA1 = 0x7a1 ,   CSR_TDATA2 = 0x7a2 , CSR_TDATA3 = 0x7a3 , CSR_TINFO = 0x7a4 , CSR_TCONTROL = 0x7a5 ,   CSR_MCONTEXT = 0x7a8 , CSR_SCONTEXT = 0x7aa , CSR_DCSR = 0x7b0 , CSR_DPC = 0x7b1 ,   CSR_DSCRATCH0 = 0x7b2 , CSR_MCYCLE = 0xb00 , CSR_MINSTRET = 0xb02 , CSR_MHPMCOUNTER3 = 0xb03 ,   CSR_MHPMCOUNTER4 = 0xb04 , CSR_MHPMCOUNTER5 = 0xb05 , CSR_MHPMCOUNTER6 = 0xb06 , CSR_MHPMCOUNTER7 = 0xb07 ,   CSR_MHPMCOUNTER8 = 0xb08 , CSR_MHPMCOUNTER9 = 0xb09 , CSR_MHPMCOUNTER10 = 0xb0a , CSR_MHPMCOUNTER11 = 0xb0b ,   CSR_MHPMCOUNTER12 = 0xb0c , CSR_MHPMCOUNTER13 = 0xb0d , CSR_MHPMCOUNTER14 = 0xb0e , CSR_MHPMCOUNTER15 = 0xb0f ,   CSR_MHPMCOUNTER16 = 0xb10 , CSR_MHPMCOUNTER17 = 0xb11 , CSR_MHPMCOUNTER18 = 0xb12 , CSR_MHPMCOUNTER19 = 0xb13 ,   CSR_MHPMCOUNTER20 = 0xb14 , CSR_MHPMCOUNTER21 = 0xb15 , CSR_MHPMCOUNTER22 = 0xb16 , CSR_MHPMCOUNTER23 = 0xb17 ,   CSR_MHPMCOUNTER24 = 0xb18 , CSR_MHPMCOUNTER25 = 0xb19 , CSR_MHPMCOUNTER26 = 0xb1a , CSR_MHPMCOUNTER27 = 0xb1b ,   CSR_MHPMCOUNTER28 = 0xb1c , CSR_MHPMCOUNTER29 = 0xb1d , CSR_MHPMCOUNTER30 = 0xb1e , CSR_MHPMCOUNTER31 = 0xb1f ,   CSR_MCYCLEH = 0xb80 , CSR_MINSTRETH = 0xb82 , CSR_MHPMCOUNTER3H = 0xb83 , CSR_MHPMCOUNTER4H = 0xb84 ,   CSR_MHPMCOUNTER5H = 0xb85 , CSR_MHPMCOUNTER6H = 0xb86 , CSR_MHPMCOUNTER7H = 0xb87 , CSR_MHPMCOUNTER8H = 0xb88 ,   CSR_MHPMCOUNTER9H = 0xb89 , CSR_MHPMCOUNTER10H = 0xb8a , CSR_MHPMCOUNTER11H = 0xb8b , CSR_MHPMCOUNTER12H = 0xb8c ,   CSR_MHPMCOUNTER13H = 0xb8d , CSR_MHPMCOUNTER14H = 0xb8e , CSR_MHPMCOUNTER15H = 0xb8f , CSR_MHPMCOUNTER16H = 0xb90 ,   CSR_MHPMCOUNTER17H = 0xb91 , CSR_MHPMCOUNTER18H = 0xb92 , CSR_MHPMCOUNTER19H = 0xb93 , CSR_MHPMCOUNTER20H = 0xb94 ,   CSR_MHPMCOUNTER21H = 0xb95 , CSR_MHPMCOUNTER22H = 0xb96 , CSR_MHPMCOUNTER23H = 0xb97 , CSR_MHPMCOUNTER24H = 0xb98 ,   CSR_MHPMCOUNTER25H = 0xb99 , CSR_MHPMCOUNTER26H = 0xb9a , CSR_MHPMCOUNTER27H = 0xb9b , CSR_MHPMCOUNTER28H = 0xb9c ,   CSR_MHPMCOUNTER29H = 0xb9d , CSR_MHPMCOUNTER30H = 0xb9e , CSR_MHPMCOUNTER31H = 0xb9f , CSR_CYCLE = 0xc00 ,   CSR_TIME = 0xc01 , CSR_INSTRET = 0xc02 , CSR_HPMCOUNTER3 = 0xc03 , CSR_HPMCOUNTER4 = 0xc04 ,   CSR_HPMCOUNTER5 = 0xc05 , CSR_HPMCOUNTER6 = 0xc06 , CSR_HPMCOUNTER7 = 0xc07 , CSR_HPMCOUNTER8 = 0xc08 ,   CSR_HPMCOUNTER9 = 0xc09 , CSR_HPMCOUNTER10 = 0xc0a , CSR_HPMCOUNTER11 = 0xc0b , CSR_HPMCOUNTER12 = 0xc0c ,   CSR_HPMCOUNTER13 = 0xc0d , CSR_HPMCOUNTER14 = 0xc0e , CSR_HPMCOUNTER15 = 0xc0f , CSR_HPMCOUNTER16 = 0xc10 ,   CSR_HPMCOUNTER17 = 0xc11 , CSR_HPMCOUNTER18 = 0xc12 , CSR_HPMCOUNTER19 = 0xc13 , CSR_HPMCOUNTER20 = 0xc14 ,   CSR_HPMCOUNTER21 = 0xc15 , CSR_HPMCOUNTER22 = 0xc16 , CSR_HPMCOUNTER23 = 0xc17 , CSR_HPMCOUNTER24 = 0xc18 ,   CSR_HPMCOUNTER25 = 0xc19 , CSR_HPMCOUNTER26 = 0xc1a , CSR_HPMCOUNTER27 = 0xc1b , CSR_HPMCOUNTER28 = 0xc1c ,   CSR_HPMCOUNTER29 = 0xc1d , CSR_HPMCOUNTER30 = 0xc1e , CSR_HPMCOUNTER31 = 0xc1f , CSR_CYCLEH = 0xc80 ,   CSR_TIMEH = 0xc81 , CSR_INSTRETH = 0xc82 , CSR_HPMCOUNTER3H = 0xc83 , CSR_HPMCOUNTER4H = 0xc84 ,   CSR_HPMCOUNTER5H = 0xc85 , CSR_HPMCOUNTER6H = 0xc86 , CSR_HPMCOUNTER7H = 0xc87 , CSR_HPMCOUNTER8H = 0xc88 ,   CSR_HPMCOUNTER9H = 0xc89 , CSR_HPMCOUNTER10H = 0xc8a , CSR_HPMCOUNTER11H = 0xc8b , CSR_HPMCOUNTER12H = 0xc8c ,   CSR_HPMCOUNTER13H = 0xc8d , CSR_HPMCOUNTER14H = 0xc8e , CSR_HPMCOUNTER15H = 0xc8f , CSR_HPMCOUNTER16H = 0xc90 ,   CSR_HPMCOUNTER17H = 0xc91 , CSR_HPMCOUNTER18H = 0xc92 , CSR_HPMCOUNTER19H = 0xc93 , CSR_HPMCOUNTER20H = 0xc94 ,   CSR_HPMCOUNTER21H = 0xc95 , CSR_HPMCOUNTER22H = 0xc96 , CSR_HPMCOUNTER23H = 0xc97 , CSR_HPMCOUNTER24H = 0xc98 ,   CSR_HPMCOUNTER25H = 0xc99 , CSR_HPMCOUNTER26H = 0xc9a , CSR_HPMCOUNTER27H = 0xc9b , CSR_HPMCOUNTER28H = 0xc9c ,   CSR_HPMCOUNTER29H = 0xc9d , CSR_HPMCOUNTER30H = 0xc9e , CSR_HPMCOUNTER31H = 0xc9f , CSR_MVENDORID = 0xf11 ,   CSR_MARCHID = 0xf12 , CSR_MIMPID = 0xf13 , CSR_MHARTID = 0xf14 , CSR_MCONFIGPTR = 0xf15 ,   CSR_MXISA = 0xfc0 }
enum	NEORV32_CSR_MSTATUS_enum {   CSR_MSTATUS_MIE = 3 , CSR_MSTATUS_MPIE = 7 , CSR_MSTATUS_MPP_L = 11 , CSR_MSTATUS_MPP_H = 12 ,   CSR_MSTATUS_MPRV = 17 , CSR_MSTATUS_TW = 21 }
enum	NEORV32_CSR_MCOUNTINHIBIT_enum {   CSR_MCOUNTINHIBIT_CY = 0 , CSR_MCOUNTINHIBIT_IR = 2 , CSR_MCOUNTINHIBIT_HPM3 = 3 , CSR_MCOUNTINHIBIT_HPM4 = 4 ,   CSR_MCOUNTINHIBIT_HPM5 = 5 , CSR_MCOUNTINHIBIT_HPM6 = 6 , CSR_MCOUNTINHIBIT_HPM7 = 7 , CSR_MCOUNTINHIBIT_HPM8 = 8 ,   CSR_MCOUNTINHIBIT_HPM9 = 9 , CSR_MCOUNTINHIBIT_HPM10 = 10 , CSR_MCOUNTINHIBIT_HPM11 = 11 , CSR_MCOUNTINHIBIT_HPM12 = 12 ,   CSR_MCOUNTINHIBIT_HPM13 = 13 , CSR_MCOUNTINHIBIT_HPM14 = 14 , CSR_MCOUNTINHIBIT_HPM15 = 15 , CSR_MCOUNTINHIBIT_HPM16 = 16 ,   CSR_MCOUNTINHIBIT_HPM17 = 17 , CSR_MCOUNTINHIBIT_HPM18 = 18 , CSR_MCOUNTINHIBIT_HPM19 = 19 , CSR_MCOUNTINHIBIT_HPM20 = 20 ,   CSR_MCOUNTINHIBIT_HPM21 = 21 , CSR_MCOUNTINHIBIT_HPM22 = 22 , CSR_MCOUNTINHIBIT_HPM23 = 23 , CSR_MCOUNTINHIBIT_HPM24 = 24 ,   CSR_MCOUNTINHIBIT_HPM25 = 25 , CSR_MCOUNTINHIBIT_HPM26 = 26 , CSR_MCOUNTINHIBIT_HPM27 = 27 , CSR_MCOUNTINHIBIT_HPM28 = 28 ,   CSR_MCOUNTINHIBIT_HPM29 = 29 , CSR_MCOUNTINHIBIT_HPM30 = 30 , CSR_MCOUNTINHIBIT_HPM31 = 31 }
enum	NEORV32_CSR_MIE_enum {   CSR_MIE_MSIE = 3 , CSR_MIE_MTIE = 7 , CSR_MIE_MEIE = 11 , CSR_MIE_FIRQ0E = 16 ,   CSR_MIE_FIRQ1E = 17 , CSR_MIE_FIRQ2E = 18 , CSR_MIE_FIRQ3E = 19 , CSR_MIE_FIRQ4E = 20 ,   CSR_MIE_FIRQ5E = 21 , CSR_MIE_FIRQ6E = 22 , CSR_MIE_FIRQ7E = 23 , CSR_MIE_FIRQ8E = 24 ,   CSR_MIE_FIRQ9E = 25 , CSR_MIE_FIRQ10E = 26 , CSR_MIE_FIRQ11E = 27 , CSR_MIE_FIRQ12E = 28 ,   CSR_MIE_FIRQ13E = 29 , CSR_MIE_FIRQ14E = 30 , CSR_MIE_FIRQ15E = 31 }
enum	NEORV32_CSR_MIP_enum {   CSR_MIP_MSIP = 3 , CSR_MIP_MTIP = 7 , CSR_MIP_MEIP = 11 , CSR_MIP_FIRQ0P = 16 ,   CSR_MIP_FIRQ1P = 17 , CSR_MIP_FIRQ2P = 18 , CSR_MIP_FIRQ3P = 19 , CSR_MIP_FIRQ4P = 20 ,   CSR_MIP_FIRQ5P = 21 , CSR_MIP_FIRQ6P = 22 , CSR_MIP_FIRQ7P = 23 , CSR_MIP_FIRQ8P = 24 ,   CSR_MIP_FIRQ9P = 25 , CSR_MIP_FIRQ10P = 26 , CSR_MIP_FIRQ11P = 27 , CSR_MIP_FIRQ12P = 28 ,   CSR_MIP_FIRQ13P = 29 , CSR_MIP_FIRQ14P = 30 , CSR_MIP_FIRQ15P = 31 }
enum	NEORV32_CSR_MISA_enum {   CSR_MISA_A = 0 , CSR_MISA_B = 1 , CSR_MISA_C = 2 , CSR_MISA_D = 3 ,   CSR_MISA_E = 4 , CSR_MISA_F = 5 , CSR_MISA_I = 8 , CSR_MISA_M = 12 ,   CSR_MISA_U = 20 , CSR_MISA_X = 23 , CSR_MISA_MXL_LO = 30 , CSR_MISA_MXL_HI = 31 }
enum	NEORV32_CSR_XISA_enum {   CSR_MXISA_ZICSR = 0 , CSR_MXISA_ZIFENCEI = 1 , CSR_MXISA_ZMMUL = 2 , CSR_MXISA_ZXCFU = 3 ,   CSR_MXISA_ZICOND = 4 , CSR_MXISA_ZFINX = 5 , CSR_MXISA_ZICNTR = 7 , CSR_MXISA_PMP = 8 ,   CSR_MXISA_ZIHPM = 9 , CSR_MXISA_SDEXT = 10 , CSR_MXISA_SDTRIG = 11 , CSR_MXISA_IS_SIM = 20 ,   CSR_MXISA_FASTMUL = 30 , CSR_MXISA_FASTSHIFT = 31 }
enum	NEORV32_HPMCNT_EVENT_enum {   HPMCNT_EVENT_CY = 0 , HPMCNT_EVENT_IR = 2 , HPMCNT_EVENT_CIR = 3 , HPMCNT_EVENT_WAIT_IF = 4 ,   HPMCNT_EVENT_WAIT_II = 5 , HPMCNT_EVENT_WAIT_MC = 6 , HPMCNT_EVENT_LOAD = 7 , HPMCNT_EVENT_STORE = 8 ,   HPMCNT_EVENT_WAIT_LS = 9 , HPMCNT_EVENT_JUMP = 10 , HPMCNT_EVENT_BRANCH = 11 , HPMCNT_EVENT_TBRANCH = 12 ,   HPMCNT_EVENT_TRAP = 13 , HPMCNT_EVENT_ILLEGAL = 14 }
enum	NEORV32_PMPCFG_ATTRIBUTES_enum {   PMPCFG_R = 0 , PMPCFG_W = 1 , PMPCFG_X = 2 , PMPCFG_A_LSB = 3 ,   PMPCFG_A_MSB = 4 , PMPCFG_L = 7 }
enum	NEORV32_PMP_MODES_enum { PMP_OFF = 0 , PMP_TOR = 1 , PMP_NA4 = 2 , PMP_NAPOT = 3 }
enum	NEORV32_EXCEPTION_CODES_enum {   TRAP_CODE_I_MISALIGNED = 0x00000000U , TRAP_CODE_I_ACCESS = 0x00000001U , TRAP_CODE_I_ILLEGAL = 0x00000002U , TRAP_CODE_BREAKPOINT = 0x00000003U ,   TRAP_CODE_L_MISALIGNED = 0x00000004U , TRAP_CODE_L_ACCESS = 0x00000005U , TRAP_CODE_S_MISALIGNED = 0x00000006U , TRAP_CODE_S_ACCESS = 0x00000007U ,   TRAP_CODE_UENV_CALL = 0x00000008U , TRAP_CODE_MENV_CALL = 0x0000000bU , TRAP_CODE_MSI = 0x80000003U , TRAP_CODE_MTI = 0x80000007U ,   TRAP_CODE_MEI = 0x8000000bU , TRAP_CODE_FIRQ_0 = 0x80000010U , TRAP_CODE_FIRQ_1 = 0x80000011U , TRAP_CODE_FIRQ_2 = 0x80000012U ,   TRAP_CODE_FIRQ_3 = 0x80000013U , TRAP_CODE_FIRQ_4 = 0x80000014U , TRAP_CODE_FIRQ_5 = 0x80000015U , TRAP_CODE_FIRQ_6 = 0x80000016U ,   TRAP_CODE_FIRQ_7 = 0x80000017U , TRAP_CODE_FIRQ_8 = 0x80000018U , TRAP_CODE_FIRQ_9 = 0x80000019U , TRAP_CODE_FIRQ_10 = 0x8000001aU ,   TRAP_CODE_FIRQ_11 = 0x8000001bU , TRAP_CODE_FIRQ_12 = 0x8000001cU , TRAP_CODE_FIRQ_13 = 0x8000001dU , TRAP_CODE_FIRQ_14 = 0x8000001eU ,   TRAP_CODE_FIRQ_15 = 0x8000001fU }

Detailed Description

Control and Status Registers (CSR) definitions.

Enumeration Type Documentation

NEORV32_CSR_enum

enum NEORV32_CSR_enum

Available CPU Control and Status Registers (CSRs)

Enumerator
CSR_FFLAGS	0x001 - fflags: Floating-point accrued exception flags
CSR_FRM	0x002 - frm: Floating-point dynamic rounding mode
CSR_FCSR	0x003 - fcsr: Floating-point control/status register (frm + fflags)
CSR_MSTATUS	0x300 - mstatus: Machine status register
CSR_MISA	0x301 - misa: CPU ISA and extensions (read-only in NEORV32)
CSR_MIE	0x304 - mie: Machine interrupt-enable register
CSR_MTVEC	0x305 - mtvec: Machine trap-handler base address (for ALL traps)
CSR_MCOUNTEREN	0x305 - mcounteren: Machine counter enable register (controls access rights from U-mode)
CSR_MENVCFG	0x30a - menvcfg: Machine environment configuration register
CSR_MSTATUSH	0x310 - mstatush: Machine status register - high word
CSR_MENVCFGH	0x31a - menvcfgh: Machine environment configuration register - high word
CSR_MCOUNTINHIBIT	0x320 - mcountinhibit: Machine counter-inhibit register
CSR_MHPMEVENT3	0x323 - mhpmevent3: Machine hardware performance monitor event selector 3
CSR_MHPMEVENT4	0x324 - mhpmevent4: Machine hardware performance monitor event selector 4
CSR_MHPMEVENT5	0x325 - mhpmevent5: Machine hardware performance monitor event selector 5
CSR_MHPMEVENT6	0x326 - mhpmevent6: Machine hardware performance monitor event selector 6
CSR_MHPMEVENT7	0x327 - mhpmevent7: Machine hardware performance monitor event selector 7
CSR_MHPMEVENT8	0x328 - mhpmevent8: Machine hardware performance monitor event selector 8
CSR_MHPMEVENT9	0x329 - mhpmevent9: Machine hardware performance monitor event selector 9
CSR_MHPMEVENT10	0x32a - mhpmevent10: Machine hardware performance monitor event selector 10
CSR_MHPMEVENT11	0x32b - mhpmevent11: Machine hardware performance monitor event selector 11
CSR_MHPMEVENT12	0x32c - mhpmevent12: Machine hardware performance monitor event selector 12
CSR_MHPMEVENT13	0x32d - mhpmevent13: Machine hardware performance monitor event selector 13
CSR_MHPMEVENT14	0x32e - mhpmevent14: Machine hardware performance monitor event selector 14
CSR_MHPMEVENT15	0x32f - mhpmevent15: Machine hardware performance monitor event selector 15
CSR_MHPMEVENT16	0x330 - mhpmevent16: Machine hardware performance monitor event selector 16
CSR_MHPMEVENT17	0x331 - mhpmevent17: Machine hardware performance monitor event selector 17
CSR_MHPMEVENT18	0x332 - mhpmevent18: Machine hardware performance monitor event selector 18
CSR_MHPMEVENT19	0x333 - mhpmevent19: Machine hardware performance monitor event selector 19
CSR_MHPMEVENT20	0x334 - mhpmevent20: Machine hardware performance monitor event selector 20
CSR_MHPMEVENT21	0x335 - mhpmevent21: Machine hardware performance monitor event selector 21
CSR_MHPMEVENT22	0x336 - mhpmevent22: Machine hardware performance monitor event selector 22
CSR_MHPMEVENT23	0x337 - mhpmevent23: Machine hardware performance monitor event selector 23
CSR_MHPMEVENT24	0x338 - mhpmevent24: Machine hardware performance monitor event selector 24
CSR_MHPMEVENT25	0x339 - mhpmevent25: Machine hardware performance monitor event selector 25
CSR_MHPMEVENT26	0x33a - mhpmevent26: Machine hardware performance monitor event selector 26
CSR_MHPMEVENT27	0x33b - mhpmevent27: Machine hardware performance monitor event selector 27
CSR_MHPMEVENT28	0x33c - mhpmevent28: Machine hardware performance monitor event selector 28
CSR_MHPMEVENT29	0x33d - mhpmevent29: Machine hardware performance monitor event selector 29
CSR_MHPMEVENT30	0x33e - mhpmevent30: Machine hardware performance monitor event selector 30
CSR_MHPMEVENT31	0x33f - mhpmevent31: Machine hardware performance monitor event selector 31
CSR_MSCRATCH	0x340 - mscratch: Machine scratch register
CSR_MEPC	0x341 - mepc: Machine exception program counter
CSR_MCAUSE	0x342 - mcause: Machine trap cause
CSR_MTVAL	0x343 - mtval: Machine trap value register
CSR_MIP	0x344 - mip: Machine interrupt pending register
CSR_PMPCFG0	0x3a0 - pmpcfg0: Physical memory protection configuration register 0 (entries 0..3)
CSR_PMPCFG1	0x3a1 - pmpcfg1: Physical memory protection configuration register 1 (entries 4..7)
CSR_PMPCFG2	0x3a2 - pmpcfg2: Physical memory protection configuration register 2 (entries 8..11)
CSR_PMPCFG3	0x3a3 - pmpcfg3: Physical memory protection configuration register 3 (entries 12..15)
CSR_PMPADDR0	0x3b0 - pmpaddr0: Physical memory protection address register 0
CSR_PMPADDR1	0x3b1 - pmpaddr1: Physical memory protection address register 1
CSR_PMPADDR2	0x3b2 - pmpaddr2: Physical memory protection address register 2
CSR_PMPADDR3	0x3b3 - pmpaddr3: Physical memory protection address register 3
CSR_PMPADDR4	0x3b4 - pmpaddr4: Physical memory protection address register 4
CSR_PMPADDR5	0x3b5 - pmpaddr5: Physical memory protection address register 5
CSR_PMPADDR6	0x3b6 - pmpaddr6: Physical memory protection address register 6
CSR_PMPADDR7	0x3b7 - pmpaddr7: Physical memory protection address register 7
CSR_PMPADDR8	0x3b8 - pmpaddr8: Physical memory protection address register 8
CSR_PMPADDR9	0x3b9 - pmpaddr9: Physical memory protection address register 9
CSR_PMPADDR10	0x3ba - pmpaddr10: Physical memory protection address register 10
CSR_PMPADDR11	0x3bb - pmpaddr11: Physical memory protection address register 11
CSR_PMPADDR12	0x3bc - pmpaddr12: Physical memory protection address register 12
CSR_PMPADDR13	0x3bd - pmpaddr13: Physical memory protection address register 13
CSR_PMPADDR14	0x3be - pmpaddr14: Physical memory protection address register 14
CSR_PMPADDR15	0x3bf - pmpaddr15: Physical memory protection address register 15
CSR_TSELECT	0x7a0 - tselect: Trigger select
CSR_TDATA1	0x7a1 - tdata1: Trigger data register 0
CSR_TDATA2	0x7a2 - tdata2: Trigger data register 1
CSR_TDATA3	0x7a3 - tdata3: Trigger data register 2
CSR_TINFO	0x7a4 - tinfo: Trigger info
CSR_TCONTROL	0x7a5 - tcontrol: Trigger control
CSR_MCONTEXT	0x7a8 - mcontext: Machine context register
CSR_SCONTEXT	0x7aa - scontext: Supervisor context register
CSR_DCSR	0x7b0 - dcsr: Debug status and control register
CSR_DPC	0x7b1 - dpc: Debug program counter
CSR_DSCRATCH0	0x7b2 - dscratch0: Debug scratch register
CSR_MCYCLE	0xb00 - mcycle: Machine cycle counter low word
CSR_MINSTRET	0xb02 - minstret: Machine instructions-retired counter low word
CSR_MHPMCOUNTER3	0xb03 - mhpmcounter3: Machine hardware performance monitor 3 counter low word
CSR_MHPMCOUNTER4	0xb04 - mhpmcounter4: Machine hardware performance monitor 4 counter low word
CSR_MHPMCOUNTER5	0xb05 - mhpmcounter5: Machine hardware performance monitor 5 counter low word
CSR_MHPMCOUNTER6	0xb06 - mhpmcounter6: Machine hardware performance monitor 6 counter low word
CSR_MHPMCOUNTER7	0xb07 - mhpmcounter7: Machine hardware performance monitor 7 counter low word
CSR_MHPMCOUNTER8	0xb08 - mhpmcounter8: Machine hardware performance monitor 8 counter low word
CSR_MHPMCOUNTER9	0xb09 - mhpmcounter9: Machine hardware performance monitor 9 counter low word
CSR_MHPMCOUNTER10	0xb0a - mhpmcounter10: Machine hardware performance monitor 10 counter low word
CSR_MHPMCOUNTER11	0xb0b - mhpmcounter11: Machine hardware performance monitor 11 counter low word
CSR_MHPMCOUNTER12	0xb0c - mhpmcounter12: Machine hardware performance monitor 12 counter low word
CSR_MHPMCOUNTER13	0xb0d - mhpmcounter13: Machine hardware performance monitor 13 counter low word
CSR_MHPMCOUNTER14	0xb0e - mhpmcounter14: Machine hardware performance monitor 14 counter low word
CSR_MHPMCOUNTER15	0xb0f - mhpmcounter15: Machine hardware performance monitor 15 counter low word
CSR_MHPMCOUNTER16	0xb10 - mhpmcounter16: Machine hardware performance monitor 16 counter low word
CSR_MHPMCOUNTER17	0xb11 - mhpmcounter17: Machine hardware performance monitor 17 counter low word
CSR_MHPMCOUNTER18	0xb12 - mhpmcounter18: Machine hardware performance monitor 18 counter low word
CSR_MHPMCOUNTER19	0xb13 - mhpmcounter19: Machine hardware performance monitor 19 counter low word
CSR_MHPMCOUNTER20	0xb14 - mhpmcounter20: Machine hardware performance monitor 20 counter low word
CSR_MHPMCOUNTER21	0xb15 - mhpmcounter21: Machine hardware performance monitor 21 counter low word
CSR_MHPMCOUNTER22	0xb16 - mhpmcounter22: Machine hardware performance monitor 22 counter low word
CSR_MHPMCOUNTER23	0xb17 - mhpmcounter23: Machine hardware performance monitor 23 counter low word
CSR_MHPMCOUNTER24	0xb18 - mhpmcounter24: Machine hardware performance monitor 24 counter low word
CSR_MHPMCOUNTER25	0xb19 - mhpmcounter25: Machine hardware performance monitor 25 counter low word
CSR_MHPMCOUNTER26	0xb1a - mhpmcounter26: Machine hardware performance monitor 26 counter low word
CSR_MHPMCOUNTER27	0xb1b - mhpmcounter27: Machine hardware performance monitor 27 counter low word
CSR_MHPMCOUNTER28	0xb1c - mhpmcounter28: Machine hardware performance monitor 28 counter low word
CSR_MHPMCOUNTER29	0xb1d - mhpmcounter29: Machine hardware performance monitor 29 counter low word
CSR_MHPMCOUNTER30	0xb1e - mhpmcounter30: Machine hardware performance monitor 30 counter low word
CSR_MHPMCOUNTER31	0xb1f - mhpmcounter31: Machine hardware performance monitor 31 counter low word
CSR_MCYCLEH	0xb80 - mcycleh: Machine cycle counter high word
CSR_MINSTRETH	0xb82 - minstreth: Machine instructions-retired counter high word
CSR_MHPMCOUNTER3H	0xb83 - mhpmcounter3 : Machine hardware performance monitor 3 counter high word
CSR_MHPMCOUNTER4H	0xb84 - mhpmcounter4h: Machine hardware performance monitor 4 counter high word
CSR_MHPMCOUNTER5H	0xb85 - mhpmcounter5h: Machine hardware performance monitor 5 counter high word
CSR_MHPMCOUNTER6H	0xb86 - mhpmcounter6h: Machine hardware performance monitor 6 counter high word
CSR_MHPMCOUNTER7H	0xb87 - mhpmcounter7h: Machine hardware performance monitor 7 counter high word
CSR_MHPMCOUNTER8H	0xb88 - mhpmcounter8h: Machine hardware performance monitor 8 counter high word
CSR_MHPMCOUNTER9H	0xb89 - mhpmcounter9h: Machine hardware performance monitor 9 counter high word
CSR_MHPMCOUNTER10H	0xb8a - mhpmcounter10h: Machine hardware performance monitor 10 counter high word
CSR_MHPMCOUNTER11H	0xb8b - mhpmcounter11h: Machine hardware performance monitor 11 counter high word
CSR_MHPMCOUNTER12H	0xb8c - mhpmcounter12h: Machine hardware performance monitor 12 counter high word
CSR_MHPMCOUNTER13H	0xb8d - mhpmcounter13h: Machine hardware performance monitor 13 counter high word
CSR_MHPMCOUNTER14H	0xb8e - mhpmcounter14h: Machine hardware performance monitor 14 counter high word
CSR_MHPMCOUNTER15H	0xb8f - mhpmcounter15h: Machine hardware performance monitor 15 counter high word
CSR_MHPMCOUNTER16H	0xb90 - mhpmcounter16h: Machine hardware performance monitor 16 counter high word
CSR_MHPMCOUNTER17H	0xb91 - mhpmcounter17h: Machine hardware performance monitor 17 counter high word
CSR_MHPMCOUNTER18H	0xb92 - mhpmcounter18h: Machine hardware performance monitor 18 counter high word
CSR_MHPMCOUNTER19H	0xb93 - mhpmcounter19h: Machine hardware performance monitor 19 counter high word
CSR_MHPMCOUNTER20H	0xb94 - mhpmcounter20h: Machine hardware performance monitor 20 counter high word
CSR_MHPMCOUNTER21H	0xb95 - mhpmcounter21h: Machine hardware performance monitor 21 counter high word
CSR_MHPMCOUNTER22H	0xb96 - mhpmcounter22h: Machine hardware performance monitor 22 counter high word
CSR_MHPMCOUNTER23H	0xb97 - mhpmcounter23h: Machine hardware performance monitor 23 counter high word
CSR_MHPMCOUNTER24H	0xb98 - mhpmcounter24h: Machine hardware performance monitor 24 counter high word
CSR_MHPMCOUNTER25H	0xb99 - mhpmcounter25h: Machine hardware performance monitor 25 counter high word
CSR_MHPMCOUNTER26H	0xb9a - mhpmcounter26h: Machine hardware performance monitor 26 counter high word
CSR_MHPMCOUNTER27H	0xb9b - mhpmcounter27h: Machine hardware performance monitor 27 counter high word
CSR_MHPMCOUNTER28H	0xb9c - mhpmcounter28h: Machine hardware performance monitor 28 counter high word
CSR_MHPMCOUNTER29H	0xb9d - mhpmcounter29h: Machine hardware performance monitor 29 counter high word
CSR_MHPMCOUNTER30H	0xb9e - mhpmcounter30h: Machine hardware performance monitor 30 counter high word
CSR_MHPMCOUNTER31H	0xb9f - mhpmcounter31h: Machine hardware performance monitor 31 counter high word
CSR_CYCLE	0xc00 - cycle: Cycle counter low word (from MCYCLE)
CSR_TIME	0xc01 - time: Time counter low word
CSR_INSTRET	0xc02 - instret: Instructions-retired counter low word (from MINSTRET)
CSR_HPMCOUNTER3	0xc03 - hpmcounter3: User hardware performance monitor 3 counter low word
CSR_HPMCOUNTER4	0xc04 - hpmcounter4: User hardware performance monitor 4 counter low word
CSR_HPMCOUNTER5	0xc05 - hpmcounter5: User hardware performance monitor 5 counter low word
CSR_HPMCOUNTER6	0xc06 - hpmcounter6: User hardware performance monitor 6 counter low word
CSR_HPMCOUNTER7	0xc07 - hpmcounter7: User hardware performance monitor 7 counter low word
CSR_HPMCOUNTER8	0xc08 - hpmcounter8: User hardware performance monitor 8 counter low word
CSR_HPMCOUNTER9	0xc09 - hpmcounter9: User hardware performance monitor 9 counter low word
CSR_HPMCOUNTER10	0xc0a - hpmcounter10: User hardware performance monitor 10 counter low word
CSR_HPMCOUNTER11	0xc0b - hpmcounter11: User hardware performance monitor 11 counter low word
CSR_HPMCOUNTER12	0xc0c - hpmcounter12: User hardware performance monitor 12 counter low word
CSR_HPMCOUNTER13	0xc0d - hpmcounter13: User hardware performance monitor 13 counter low word
CSR_HPMCOUNTER14	0xc0e - hpmcounter14: User hardware performance monitor 14 counter low word
CSR_HPMCOUNTER15	0xc0f - hpmcounter15: User hardware performance monitor 15 counter low word
CSR_HPMCOUNTER16	0xc10 - hpmcounter16: User hardware performance monitor 16 counter low word
CSR_HPMCOUNTER17	0xc11 - hpmcounter17: User hardware performance monitor 17 counter low word
CSR_HPMCOUNTER18	0xc12 - hpmcounter18: User hardware performance monitor 18 counter low word
CSR_HPMCOUNTER19	0xc13 - hpmcounter19: User hardware performance monitor 19 counter low word
CSR_HPMCOUNTER20	0xc14 - hpmcounter20: User hardware performance monitor 20 counter low word
CSR_HPMCOUNTER21	0xc15 - hpmcounter21: User hardware performance monitor 21 counter low word
CSR_HPMCOUNTER22	0xc16 - hpmcounter22: User hardware performance monitor 22 counter low word
CSR_HPMCOUNTER23	0xc17 - hpmcounter23: User hardware performance monitor 23 counter low word
CSR_HPMCOUNTER24	0xc18 - hpmcounter24: User hardware performance monitor 24 counter low word
CSR_HPMCOUNTER25	0xc19 - hpmcounter25: User hardware performance monitor 25 counter low word
CSR_HPMCOUNTER26	0xc1a - hpmcounter26: User hardware performance monitor 26 counter low word
CSR_HPMCOUNTER27	0xc1b - hpmcounter27: User hardware performance monitor 27 counter low word
CSR_HPMCOUNTER28	0xc1c - hpmcounter28: User hardware performance monitor 28 counter low word
CSR_HPMCOUNTER29	0xc1d - hpmcounter29: User hardware performance monitor 29 counter low word
CSR_HPMCOUNTER30	0xc1e - hpmcounter30: User hardware performance monitor 30 counter low word
CSR_HPMCOUNTER31	0xc1f - hpmcounter31: User hardware performance monitor 31 counter low word
CSR_CYCLEH	0xc80 - cycleh: Cycle counter high word (from MCYCLEH)
CSR_TIMEH	0xc81 - timeh: Time counter high word
CSR_INSTRETH	0xc82 - instreth: Instructions-retired counter high word (from MINSTRETH)
CSR_HPMCOUNTER3H	0xc83 - hpmcounter3h: User hardware performance monitor 3 counter high word
CSR_HPMCOUNTER4H	0xc84 - hpmcounter4h: User hardware performance monitor 4 counter high word
CSR_HPMCOUNTER5H	0xc85 - hpmcounter5h: User hardware performance monitor 5 counter high word
CSR_HPMCOUNTER6H	0xc86 - hpmcounter6h: User hardware performance monitor 6 counter high word
CSR_HPMCOUNTER7H	0xc87 - hpmcounter7h: User hardware performance monitor 7 counter high word
CSR_HPMCOUNTER8H	0xc88 - hpmcounter8h: User hardware performance monitor 8 counter high word
CSR_HPMCOUNTER9H	0xc89 - hpmcounter9h: User hardware performance monitor 9 counter high word
CSR_HPMCOUNTER10H	0xc8a - hpmcounter10h: User hardware performance monitor 10 counter high word
CSR_HPMCOUNTER11H	0xc8b - hpmcounter11h: User hardware performance monitor 11 counter high word
CSR_HPMCOUNTER12H	0xc8c - hpmcounter12h: User hardware performance monitor 12 counter high word
CSR_HPMCOUNTER13H	0xc8d - hpmcounter13h: User hardware performance monitor 13 counter high word
CSR_HPMCOUNTER14H	0xc8e - hpmcounter14h: User hardware performance monitor 14 counter high word
CSR_HPMCOUNTER15H	0xc8f - hpmcounter15h: User hardware performance monitor 15 counter high word
CSR_HPMCOUNTER16H	0xc90 - hpmcounter16h: User hardware performance monitor 16 counter high word
CSR_HPMCOUNTER17H	0xc91 - hpmcounter17h: User hardware performance monitor 17 counter high word
CSR_HPMCOUNTER18H	0xc92 - hpmcounter18h: User hardware performance monitor 18 counter high word
CSR_HPMCOUNTER19H	0xc93 - hpmcounter19h: User hardware performance monitor 19 counter high word
CSR_HPMCOUNTER20H	0xc94 - hpmcounter20h: User hardware performance monitor 20 counter high word
CSR_HPMCOUNTER21H	0xc95 - hpmcounter21h: User hardware performance monitor 21 counter high word
CSR_HPMCOUNTER22H	0xc96 - hpmcounter22h: User hardware performance monitor 22 counter high word
CSR_HPMCOUNTER23H	0xc97 - hpmcounter23h: User hardware performance monitor 23 counter high word
CSR_HPMCOUNTER24H	0xc98 - hpmcounter24h: User hardware performance monitor 24 counter high word
CSR_HPMCOUNTER25H	0xc99 - hpmcounter25h: User hardware performance monitor 25 counter high word
CSR_HPMCOUNTER26H	0xc9a - hpmcounter26h: User hardware performance monitor 26 counter high word
CSR_HPMCOUNTER27H	0xc9b - hpmcounter27h: User hardware performance monitor 27 counter high word
CSR_HPMCOUNTER28H	0xc9c - hpmcounter28h: User hardware performance monitor 28 counter high word
CSR_HPMCOUNTER29H	0xc9d - hpmcounter29h: User hardware performance monitor 29 counter high word
CSR_HPMCOUNTER30H	0xc9e - hpmcounter30h: User hardware performance monitor 30 counter high word
CSR_HPMCOUNTER31H	0xc9f - hpmcounter31h: User hardware performance monitor 31 counter high word
CSR_MVENDORID	0xf11 - mvendorid: Vendor ID
CSR_MARCHID	0xf12 - marchid: Architecture ID
CSR_MIMPID	0xf13 - mimpid: Implementation ID/version
CSR_MHARTID	0xf14 - mhartid: Hardware thread ID (always 0)
CSR_MCONFIGPTR	0xf15 - mconfigptr: Machine configuration pointer register
CSR_MXISA	0xfc0 - mxisa: NEORV32-specific machine "extended CPU ISA and extensions"

NEORV32_CSR_MCOUNTINHIBIT_enum

enum NEORV32_CSR_MCOUNTINHIBIT_enum

CPU mcountinhibit CSR (r/w): Machine counter-inhibit

Enumerator
CSR_MCOUNTINHIBIT_CY	CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h] CSR when set (r/w)
CSR_MCOUNTINHIBIT_IR	CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w)
CSR_MCOUNTINHIBIT_HPM3	CPU mcountinhibit CSR (3): HPM3 - Enable auto-increment of hpmcnt3[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM4	CPU mcountinhibit CSR (4): HPM4 - Enable auto-increment of hpmcnt4[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM5	CPU mcountinhibit CSR (5): HPM5 - Enable auto-increment of hpmcnt5[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM6	CPU mcountinhibit CSR (6): HPM6 - Enable auto-increment of hpmcnt6[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM7	CPU mcountinhibit CSR (7): HPM7 - Enable auto-increment of hpmcnt7[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM8	CPU mcountinhibit CSR (8): HPM8 - Enable auto-increment of hpmcnt8[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM9	CPU mcountinhibit CSR (9): HPM9 - Enable auto-increment of hpmcnt9[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM10	CPU mcountinhibit CSR (10): HPM10 - Enable auto-increment of hpmcnt10[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM11	CPU mcountinhibit CSR (11): HPM11 - Enable auto-increment of hpmcnt11[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM12	CPU mcountinhibit CSR (12): HPM12 - Enable auto-increment of hpmcnt12[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM13	CPU mcountinhibit CSR (13): HPM13 - Enable auto-increment of hpmcnt13[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM14	CPU mcountinhibit CSR (14): HPM14 - Enable auto-increment of hpmcnt14[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM15	CPU mcountinhibit CSR (15): HPM15 - Enable auto-increment of hpmcnt15[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM16	CPU mcountinhibit CSR (16): HPM16 - Enable auto-increment of hpmcnt16[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM17	CPU mcountinhibit CSR (17): HPM17 - Enable auto-increment of hpmcnt17[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM18	CPU mcountinhibit CSR (18): HPM18 - Enable auto-increment of hpmcnt18[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM19	CPU mcountinhibit CSR (19): HPM19 - Enable auto-increment of hpmcnt19[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM20	CPU mcountinhibit CSR (20): HPM20 - Enable auto-increment of hpmcnt20[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM21	CPU mcountinhibit CSR (21): HPM21 - Enable auto-increment of hpmcnt21[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM22	CPU mcountinhibit CSR (22): HPM22 - Enable auto-increment of hpmcnt22[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM23	CPU mcountinhibit CSR (23): HPM23 - Enable auto-increment of hpmcnt23[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM24	CPU mcountinhibit CSR (24): HPM24 - Enable auto-increment of hpmcnt24[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM25	CPU mcountinhibit CSR (25): HPM25 - Enable auto-increment of hpmcnt25[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM26	CPU mcountinhibit CSR (26): HPM26 - Enable auto-increment of hpmcnt26[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM27	CPU mcountinhibit CSR (27): HPM27 - Enable auto-increment of hpmcnt27[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM28	CPU mcountinhibit CSR (28): HPM28 - Enable auto-increment of hpmcnt28[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM29	CPU mcountinhibit CSR (29): HPM29 - Enable auto-increment of hpmcnt29[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM30	CPU mcountinhibit CSR (30): HPM30 - Enable auto-increment of hpmcnt30[h] when set (r/w)
CSR_MCOUNTINHIBIT_HPM31	CPU mcountinhibit CSR (31): HPM31 - Enable auto-increment of hpmcnt31[h] when set (r/w)

NEORV32_CSR_MIE_enum

enum NEORV32_CSR_MIE_enum

CPU mie CSR (r/w): Machine interrupt enable

Enumerator
CSR_MIE_MSIE	CPU mie CSR (3): MSIE - Machine software interrupt enable (r/w)
CSR_MIE_MTIE	CPU mie CSR (7): MTIE - Machine timer interrupt enable bit (r/w)
CSR_MIE_MEIE	CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w)
CSR_MIE_FIRQ0E	CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w)
CSR_MIE_FIRQ1E	CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w)
CSR_MIE_FIRQ2E	CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w)
CSR_MIE_FIRQ3E	CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w)
CSR_MIE_FIRQ4E	CPU mie CSR (20): FIRQ4E - Fast interrupt channel 4 enable bit (r/w)
CSR_MIE_FIRQ5E	CPU mie CSR (21): FIRQ5E - Fast interrupt channel 5 enable bit (r/w)
CSR_MIE_FIRQ6E	CPU mie CSR (22): FIRQ6E - Fast interrupt channel 6 enable bit (r/w)
CSR_MIE_FIRQ7E	CPU mie CSR (23): FIRQ7E - Fast interrupt channel 7 enable bit (r/w)
CSR_MIE_FIRQ8E	CPU mie CSR (24): FIRQ8E - Fast interrupt channel 8 enable bit (r/w)
CSR_MIE_FIRQ9E	CPU mie CSR (25): FIRQ9E - Fast interrupt channel 9 enable bit (r/w)
CSR_MIE_FIRQ10E	CPU mie CSR (26): FIRQ10E - Fast interrupt channel 10 enable bit (r/w)
CSR_MIE_FIRQ11E	CPU mie CSR (27): FIRQ11E - Fast interrupt channel 11 enable bit (r/w)
CSR_MIE_FIRQ12E	CPU mie CSR (28): FIRQ12E - Fast interrupt channel 12 enable bit (r/w)
CSR_MIE_FIRQ13E	CPU mie CSR (29): FIRQ13E - Fast interrupt channel 13 enable bit (r/w)
CSR_MIE_FIRQ14E	CPU mie CSR (30): FIRQ14E - Fast interrupt channel 14 enable bit (r/w)
CSR_MIE_FIRQ15E	CPU mie CSR (31): FIRQ15E - Fast interrupt channel 15 enable bit (r/w)

NEORV32_CSR_MIP_enum

enum NEORV32_CSR_MIP_enum

CPU mip CSR (r/c): Machine interrupt pending

Enumerator
CSR_MIP_MSIP	CPU mip CSR (3): MSIP - Machine software interrupt pending (r/c)
CSR_MIP_MTIP	CPU mip CSR (7): MTIP - Machine timer interrupt pending (r/c)
CSR_MIP_MEIP	CPU mip CSR (11): MEIP - Machine external interrupt pending (r/c)
CSR_MIP_FIRQ0P	CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/c)
CSR_MIP_FIRQ1P	CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/c)
CSR_MIP_FIRQ2P	CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/c)
CSR_MIP_FIRQ3P	CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/c)
CSR_MIP_FIRQ4P	CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/c)
CSR_MIP_FIRQ5P	CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/c)
CSR_MIP_FIRQ6P	CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/c)
CSR_MIP_FIRQ7P	CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/c)
CSR_MIP_FIRQ8P	CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/c)
CSR_MIP_FIRQ9P	CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/c)
CSR_MIP_FIRQ10P	CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/c)
CSR_MIP_FIRQ11P	CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/c)
CSR_MIP_FIRQ12P	CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/c)
CSR_MIP_FIRQ13P	CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/c)
CSR_MIP_FIRQ14P	CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/c)
CSR_MIP_FIRQ15P	CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/c)

NEORV32_CSR_MISA_enum

enum NEORV32_CSR_MISA_enum

CPU misa CSR (r/-): Machine instruction set extensions

Enumerator
CSR_MISA_A	CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)
CSR_MISA_B	CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)
CSR_MISA_C	CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)
CSR_MISA_D	CPU misa CSR (3): D: Double-precision floating-point extension available (r/-)
CSR_MISA_E	CPU misa CSR (4): E: Embedded CPU extension available (r/-)
CSR_MISA_F	CPU misa CSR (5): F: Single-precision floating-point extension available (r/-)
CSR_MISA_I	CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-)
CSR_MISA_M	CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)
CSR_MISA_U	CPU misa CSR (20): U: User mode CPU extension available (r/-)
CSR_MISA_X	CPU misa CSR (23): X: Non-standard CPU extension available (r/-)
CSR_MISA_MXL_LO	CPU misa CSR (30): MXL.lo: CPU data width (r/-)
CSR_MISA_MXL_HI	CPU misa CSR (31): MXL.Hi: CPU data width (r/-)

NEORV32_CSR_MSTATUS_enum

enum NEORV32_CSR_MSTATUS_enum

CPU mstatus CSR (r/w): Machine status

Enumerator
CSR_MSTATUS_MIE	CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w)
CSR_MSTATUS_MPIE	CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w)
CSR_MSTATUS_MPP_L	CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w)
CSR_MSTATUS_MPP_H	CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w)
CSR_MSTATUS_MPRV	CPU mstatus CSR (17): MPRV - Use MPP as effective privilege for M-mode load/stores when set (r/w)
CSR_MSTATUS_TW	CPU mstatus CSR (21): TW - Disallow execution of wfi instruction in user mode when set (r/w)

NEORV32_CSR_XISA_enum

enum NEORV32_CSR_XISA_enum

CPU mxisa CSR (r/-): Machine extended instruction set extensions (NEORV32-specific)

Enumerator
CSR_MXISA_ZICSR	CPU mxisa CSR (0): privileged architecture (r/-)
CSR_MXISA_ZIFENCEI	CPU mxisa CSR (1): instruction stream sync (r/-)
CSR_MXISA_ZMMUL	CPU mxisa CSR (2): hardware mul/div (r/-)
CSR_MXISA_ZXCFU	CPU mxisa CSR (3): custom RISC-V instructions (r/-)
CSR_MXISA_ZICOND	CPU mxisa CSR (4): conditional operations (r/-)
CSR_MXISA_ZFINX	CPU mxisa CSR (5): FPU using x registers, "F-alternative" (r/-)
CSR_MXISA_ZICNTR	CPU mxisa CSR (7): standard instruction, cycle and time counter CSRs (r/-)
CSR_MXISA_PMP	CPU mxisa CSR (8): physical memory protection (also "Smpmp") (r/-)
CSR_MXISA_ZIHPM	CPU mxisa CSR (9): hardware performance monitors (r/-)
CSR_MXISA_SDEXT	CPU mxisa CSR (10): RISC-V debug mode (r/-)
CSR_MXISA_SDTRIG	CPU mxisa CSR (11): RISC-V trigger module (r/-)
CSR_MXISA_IS_SIM	CPU mxisa CSR (20): this might be a simulation when set (r/-)
CSR_MXISA_FASTMUL	CPU mxisa CSR (30): DSP-based multiplication (M extensions only) (r/-)
CSR_MXISA_FASTSHIFT	CPU mxisa CSR (31): parallel logic for shifts (barrel shifters) (r/-)

NEORV32_EXCEPTION_CODES_enum

enum NEORV32_EXCEPTION_CODES_enum

Trap codes from mcause CSR.

Enumerator
TRAP_CODE_I_MISALIGNED	0.0: Instruction address misaligned
TRAP_CODE_I_ACCESS	0.1: Instruction (bus) access fault
TRAP_CODE_I_ILLEGAL	0.2: Illegal instruction
TRAP_CODE_BREAKPOINT	0.3: Breakpoint (EBREAK instruction)
TRAP_CODE_L_MISALIGNED	0.4: Load address misaligned
TRAP_CODE_L_ACCESS	0.5: Load (bus) access fault
TRAP_CODE_S_MISALIGNED	0.6: Store address misaligned
TRAP_CODE_S_ACCESS	0.7: Store (bus) access fault
TRAP_CODE_UENV_CALL	0.8: Environment call from user mode (ECALL instruction)
TRAP_CODE_MENV_CALL	0.11: Environment call from machine mode (ECALL instruction)
TRAP_CODE_MSI	1.3: Machine software interrupt
TRAP_CODE_MTI	1.7: Machine timer interrupt
TRAP_CODE_MEI	1.11: Machine external interrupt
TRAP_CODE_FIRQ_0	1.16: Fast interrupt channel 0
TRAP_CODE_FIRQ_1	1.17: Fast interrupt channel 1
TRAP_CODE_FIRQ_2	1.18: Fast interrupt channel 2
TRAP_CODE_FIRQ_3	1.19: Fast interrupt channel 3
TRAP_CODE_FIRQ_4	1.20: Fast interrupt channel 4
TRAP_CODE_FIRQ_5	1.21: Fast interrupt channel 5
TRAP_CODE_FIRQ_6	1.22: Fast interrupt channel 6
TRAP_CODE_FIRQ_7	1.23: Fast interrupt channel 7
TRAP_CODE_FIRQ_8	1.24: Fast interrupt channel 8
TRAP_CODE_FIRQ_9	1.25: Fast interrupt channel 9
TRAP_CODE_FIRQ_10	1.26: Fast interrupt channel 10
TRAP_CODE_FIRQ_11	1.27: Fast interrupt channel 11
TRAP_CODE_FIRQ_12	1.28: Fast interrupt channel 12
TRAP_CODE_FIRQ_13	1.29: Fast interrupt channel 13
TRAP_CODE_FIRQ_14	1.30: Fast interrupt channel 14
TRAP_CODE_FIRQ_15	1.31: Fast interrupt channel 15

NEORV32_HPMCNT_EVENT_enum

enum NEORV32_HPMCNT_EVENT_enum

CPU mhpmevent hardware performance monitor events

Enumerator
HPMCNT_EVENT_CY	CPU mhpmevent CSR (0): Active cycle
HPMCNT_EVENT_IR	CPU mhpmevent CSR (2): Retired instruction
HPMCNT_EVENT_CIR	CPU mhpmevent CSR (3): Retired compressed instruction
HPMCNT_EVENT_WAIT_IF	CPU mhpmevent CSR (4): Instruction fetch memory wait cycle
HPMCNT_EVENT_WAIT_II	CPU mhpmevent CSR (5): Instruction issue wait cycle
HPMCNT_EVENT_WAIT_MC	CPU mhpmevent CSR (6): Multi-cycle ALU-operation wait cycle
HPMCNT_EVENT_LOAD	CPU mhpmevent CSR (7): Load operation
HPMCNT_EVENT_STORE	CPU mhpmevent CSR (8): Store operation
HPMCNT_EVENT_WAIT_LS	CPU mhpmevent CSR (9): Load/store memory wait cycle
HPMCNT_EVENT_JUMP	CPU mhpmevent CSR (10): Unconditional jump
HPMCNT_EVENT_BRANCH	CPU mhpmevent CSR (11): Conditional branch (taken or not taken)
HPMCNT_EVENT_TBRANCH	CPU mhpmevent CSR (12): Conditional taken branch
HPMCNT_EVENT_TRAP	CPU mhpmevent CSR (13): Entered trap
HPMCNT_EVENT_ILLEGAL	CPU mhpmevent CSR (14): Illegal instruction exception

NEORV32_PMP_MODES_enum

enum NEORV32_PMP_MODES_enum

PMP modes

Enumerator
PMP_OFF	'00': entry disabled
PMP_TOR	'01': TOR mode (top of region)
PMP_NA4	'10': Naturally-aligned power of two region (4 bytes)
PMP_NAPOT	'11': Naturally-aligned power of two region (greater than 4 bytes )

NEORV32_PMPCFG_ATTRIBUTES_enum

enum NEORV32_PMPCFG_ATTRIBUTES_enum

CPU pmpcfg PMP configuration attributes

Enumerator
PMPCFG_R	CPU pmpcfg attribute (0): Read
PMPCFG_W	CPU pmpcfg attribute (1): Write
PMPCFG_X	CPU pmpcfg attribute (2): Execute
PMPCFG_A_LSB	CPU pmpcfg attribute (3): Mode LSB NEORV32_PMP_MODES_enum
PMPCFG_A_MSB	CPU pmpcfg attribute (4): Mode MSB NEORV32_PMP_MODES_enum
PMPCFG_L	CPU pmpcfg attribute (7): Locked