neorv32_cpu_csr.h

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// #################################################################################################
// # << NEORV32: neorv32_cpu_csr.h - Control and Status Registers Definitions >>                   #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved.                                     #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************/
#ifndef neorv32_cpu_csr_h
#define neorv32_cpu_csr_h
 
 
/**********************************************************************/
enum NEORV32_CSR_enum {
  /* floating-point unit control and status */
  CSR_FFLAGS         = 0x001, 
  CSR_FRM            = 0x002, 
  CSR_FCSR           = 0x003, 
  /* machine control and status */
  CSR_MSTATUS        = 0x300, 
  CSR_MISA           = 0x301, 
  CSR_MIE            = 0x304, 
  CSR_MTVEC          = 0x305, 
  CSR_MCOUNTEREN     = 0x306, 
  CSR_MSTATUSH       = 0x310, 
  CSR_MCOUNTINHIBIT  = 0x320, 
  CSR_MCYCLECFG      = 0x321, 
  CSR_MINSTRETCFG    = 0x322, 
  /* machine configuration */
  CSR_MENVCFG        = 0x30a, 
  CSR_MENVCFGH       = 0x31a, 
  /* hardware performance monitors - event configuration */
  CSR_MHPMEVENT3     = 0x323, 
  CSR_MHPMEVENT4     = 0x324, 
  CSR_MHPMEVENT5     = 0x325, 
  CSR_MHPMEVENT6     = 0x326, 
  CSR_MHPMEVENT7     = 0x327, 
  CSR_MHPMEVENT8     = 0x328, 
  CSR_MHPMEVENT9     = 0x329, 
  CSR_MHPMEVENT10    = 0x32a, 
  CSR_MHPMEVENT11    = 0x32b, 
  CSR_MHPMEVENT12    = 0x32c, 
  CSR_MHPMEVENT13    = 0x32d, 
  CSR_MHPMEVENT14    = 0x32e, 
  CSR_MHPMEVENT15    = 0x32f, 
  /* machine trap control */
  CSR_MSCRATCH       = 0x340, 
  CSR_MEPC           = 0x341, 
  CSR_MCAUSE         = 0x342, 
  CSR_MTVAL          = 0x343, 
  CSR_MIP            = 0x344, 
  CSR_MTINST         = 0x34a, 
  /* physical memory protection */
  CSR_PMPCFG0        = 0x3a0, 
  CSR_PMPCFG1        = 0x3a1, 
  CSR_PMPCFG2        = 0x3a2, 
  CSR_PMPCFG3        = 0x3a3, 
  CSR_PMPADDR0       = 0x3b0, 
  CSR_PMPADDR1       = 0x3b1, 
  CSR_PMPADDR2       = 0x3b2, 
  CSR_PMPADDR3       = 0x3b3, 
  CSR_PMPADDR4       = 0x3b4, 
  CSR_PMPADDR5       = 0x3b5, 
  CSR_PMPADDR6       = 0x3b6, 
  CSR_PMPADDR7       = 0x3b7, 
  CSR_PMPADDR8       = 0x3b8, 
  CSR_PMPADDR9       = 0x3b9, 
  CSR_PMPADDR10      = 0x3ba, 
  CSR_PMPADDR11      = 0x3bb, 
  CSR_PMPADDR12      = 0x3bc, 
  CSR_PMPADDR13      = 0x3bd, 
  CSR_PMPADDR14      = 0x3be, 
  CSR_PMPADDR15      = 0x3bf, 
  /* machine control and status - continued */
  CSR_MCYCLECFGH     = 0x721, 
  CSR_MINSTRETCFGH   = 0x722, 
  /* on-chip debugger - hardware trigger module */
  CSR_TSELECT        = 0x7a0, 
  CSR_TDATA1         = 0x7a1, 
  CSR_TDATA2         = 0x7a2, 
  CSR_TINFO          = 0x7a4, 
  /* CPU debug mode CSRs - not accessible by software running outside of debug mode */
  CSR_DCSR           = 0x7b0, 
  CSR_DPC            = 0x7b1, 
  CSR_DSCRATCH0      = 0x7b2, 
  /* custom functions unit (CFU) registers */
  CSR_CFUREG0        = 0x800, 
  CSR_CFUREG1        = 0x801, 
  CSR_CFUREG2        = 0x802, 
  CSR_CFUREG3        = 0x803, 
  /* machine counters and timers */
  CSR_MCYCLE         = 0xb00, 
  CSR_MINSTRET       = 0xb02, 
  CSR_MHPMCOUNTER3   = 0xb03, 
  CSR_MHPMCOUNTER4   = 0xb04, 
  CSR_MHPMCOUNTER5   = 0xb05, 
  CSR_MHPMCOUNTER6   = 0xb06, 
  CSR_MHPMCOUNTER7   = 0xb07, 
  CSR_MHPMCOUNTER8   = 0xb08, 
  CSR_MHPMCOUNTER9   = 0xb09, 
  CSR_MHPMCOUNTER10  = 0xb0a, 
  CSR_MHPMCOUNTER11  = 0xb0b, 
  CSR_MHPMCOUNTER12  = 0xb0c, 
  CSR_MHPMCOUNTER13  = 0xb0d, 
  CSR_MHPMCOUNTER14  = 0xb0e, 
  CSR_MHPMCOUNTER15  = 0xb0f, 
  CSR_MCYCLEH        = 0xb80, 
  CSR_MINSTRETH      = 0xb82, 
  CSR_MHPMCOUNTER3H  = 0xb83, 
  CSR_MHPMCOUNTER4H  = 0xb84, 
  CSR_MHPMCOUNTER5H  = 0xb85, 
  CSR_MHPMCOUNTER6H  = 0xb86, 
  CSR_MHPMCOUNTER7H  = 0xb87, 
  CSR_MHPMCOUNTER8H  = 0xb88, 
  CSR_MHPMCOUNTER9H  = 0xb89, 
  CSR_MHPMCOUNTER10H = 0xb8a, 
  CSR_MHPMCOUNTER11H = 0xb8b, 
  CSR_MHPMCOUNTER12H = 0xb8c, 
  CSR_MHPMCOUNTER13H = 0xb8d, 
  CSR_MHPMCOUNTER14H = 0xb8e, 
  CSR_MHPMCOUNTER15H = 0xb8f, 
  /* user counters and timers */
  CSR_CYCLE          = 0xc00, 
  CSR_INSTRET        = 0xc02, 
  CSR_HPMCOUNTER3    = 0xc03, 
  CSR_HPMCOUNTER4    = 0xc04, 
  CSR_HPMCOUNTER5    = 0xc05, 
  CSR_HPMCOUNTER6    = 0xc06, 
  CSR_HPMCOUNTER7    = 0xc07, 
  CSR_HPMCOUNTER8    = 0xc08, 
  CSR_HPMCOUNTER9    = 0xc09, 
  CSR_HPMCOUNTER10   = 0xc0a, 
  CSR_HPMCOUNTER11   = 0xc0b, 
  CSR_HPMCOUNTER12   = 0xc0c, 
  CSR_HPMCOUNTER13   = 0xc0d, 
  CSR_HPMCOUNTER14   = 0xc0e, 
  CSR_HPMCOUNTER15   = 0xc0f, 
  CSR_CYCLEH         = 0xc80, 
  CSR_INSTRETH       = 0xc82, 
  CSR_HPMCOUNTER3H   = 0xc83, 
  CSR_HPMCOUNTER4H   = 0xc84, 
  CSR_HPMCOUNTER5H   = 0xc85, 
  CSR_HPMCOUNTER6H   = 0xc86, 
  CSR_HPMCOUNTER7H   = 0xc87, 
  CSR_HPMCOUNTER8H   = 0xc88, 
  CSR_HPMCOUNTER9H   = 0xc89, 
  CSR_HPMCOUNTER10H  = 0xc8a, 
  CSR_HPMCOUNTER11H  = 0xc8b, 
  CSR_HPMCOUNTER12H  = 0xc8c, 
  CSR_HPMCOUNTER13H  = 0xc8d, 
  CSR_HPMCOUNTER14H  = 0xc8e, 
  CSR_HPMCOUNTER15H  = 0xc8f, 
  /* machine information registers */
  CSR_MVENDORID      = 0xf11, 
  CSR_MARCHID        = 0xf12, 
  CSR_MIMPID         = 0xf13, 
  CSR_MHARTID        = 0xf14, 
  CSR_MCONFIGPTR     = 0xf15, 
  CSR_MXISA          = 0xfc0  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_FFLAGS_enum {
  CSR_FFLAGS_NX = 0, 
  CSR_FFLAGS_UF = 1, 
  CSR_FFLAGS_OF = 2, 
  CSR_FFLAGS_DZ = 3, 
  CSR_FFLAGS_NV = 4  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MSTATUS_enum {
  CSR_MSTATUS_MIE   =  3, 
  CSR_MSTATUS_MPIE  =  7, 
  CSR_MSTATUS_MPP_L = 11, 
  CSR_MSTATUS_MPP_H = 12, 
  CSR_MSTATUS_MPRV  = 17, 
  CSR_MSTATUS_TW    = 21  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MCOUNTINHIBIT_enum {
  CSR_MCOUNTINHIBIT_CY    = 0,  
  CSR_MCOUNTINHIBIT_IR    = 2,  
  CSR_MCOUNTINHIBIT_HPM3  = 3,  
  CSR_MCOUNTINHIBIT_HPM4  = 4,  
  CSR_MCOUNTINHIBIT_HPM5  = 5,  
  CSR_MCOUNTINHIBIT_HPM6  = 6,  
  CSR_MCOUNTINHIBIT_HPM7  = 7,  
  CSR_MCOUNTINHIBIT_HPM8  = 8,  
  CSR_MCOUNTINHIBIT_HPM9  = 9,  
  CSR_MCOUNTINHIBIT_HPM10 = 10, 
  CSR_MCOUNTINHIBIT_HPM11 = 11, 
  CSR_MCOUNTINHIBIT_HPM12 = 12, 
  CSR_MCOUNTINHIBIT_HPM13 = 13, 
  CSR_MCOUNTINHIBIT_HPM14 = 14, 
  CSR_MCOUNTINHIBIT_HPM15 = 15, 
  CSR_MCOUNTINHIBIT_HPM16 = 16, 
  CSR_MCOUNTINHIBIT_HPM17 = 17, 
  CSR_MCOUNTINHIBIT_HPM18 = 18, 
  CSR_MCOUNTINHIBIT_HPM19 = 19, 
  CSR_MCOUNTINHIBIT_HPM20 = 20, 
  CSR_MCOUNTINHIBIT_HPM21 = 21, 
  CSR_MCOUNTINHIBIT_HPM22 = 22, 
  CSR_MCOUNTINHIBIT_HPM23 = 23, 
  CSR_MCOUNTINHIBIT_HPM24 = 24, 
  CSR_MCOUNTINHIBIT_HPM25 = 25, 
  CSR_MCOUNTINHIBIT_HPM26 = 26, 
  CSR_MCOUNTINHIBIT_HPM27 = 27, 
  CSR_MCOUNTINHIBIT_HPM28 = 28, 
  CSR_MCOUNTINHIBIT_HPM29 = 29, 
  CSR_MCOUNTINHIBIT_HPM30 = 30, 
  CSR_MCOUNTINHIBIT_HPM31 = 31  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MCYCLECFGH_enum {
  CSR_MCYCLECFGH_UINH = 28, 
  CSR_MCYCLECFGH_MINH = 30  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MINSTRETCFGH_enum {
  CSR_MINSTRETCFGH_UINH = 28, 
  CSR_MINSTRETCFGH_MINH = 30  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MIE_enum {
  CSR_MIE_MSIE    =  3, 
  CSR_MIE_MTIE    =  7, 
  CSR_MIE_MEIE    = 11, 
  /* NEORV32-specific extension: Fast Interrupt Requests (FIRQ) */
  CSR_MIE_FIRQ0E  = 16, 
  CSR_MIE_FIRQ1E  = 17, 
  CSR_MIE_FIRQ2E  = 18, 
  CSR_MIE_FIRQ3E  = 19, 
  CSR_MIE_FIRQ4E  = 20, 
  CSR_MIE_FIRQ5E  = 21, 
  CSR_MIE_FIRQ6E  = 22, 
  CSR_MIE_FIRQ7E  = 23, 
  CSR_MIE_FIRQ8E  = 24, 
  CSR_MIE_FIRQ9E  = 25, 
  CSR_MIE_FIRQ10E = 26, 
  CSR_MIE_FIRQ11E = 27, 
  CSR_MIE_FIRQ12E = 28, 
  CSR_MIE_FIRQ13E = 29, 
  CSR_MIE_FIRQ14E = 30, 
  CSR_MIE_FIRQ15E = 31  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MIP_enum {
  CSR_MIP_MSIP    =  3, 
  CSR_MIP_MTIP    =  7, 
  CSR_MIP_MEIP    = 11, 
  /* NEORV32-specific extension: Fast Interrupt Requests (FIRQ) */
  CSR_MIP_FIRQ0P  = 16, 
  CSR_MIP_FIRQ1P  = 17, 
  CSR_MIP_FIRQ2P  = 18, 
  CSR_MIP_FIRQ3P  = 19, 
  CSR_MIP_FIRQ4P  = 20, 
  CSR_MIP_FIRQ5P  = 21, 
  CSR_MIP_FIRQ6P  = 22, 
  CSR_MIP_FIRQ7P  = 23, 
  CSR_MIP_FIRQ8P  = 24, 
  CSR_MIP_FIRQ9P  = 25, 
  CSR_MIP_FIRQ10P = 26, 
  CSR_MIP_FIRQ11P = 27, 
  CSR_MIP_FIRQ12P = 28, 
  CSR_MIP_FIRQ13P = 29, 
  CSR_MIP_FIRQ14P = 30, 
  CSR_MIP_FIRQ15P = 31  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MISA_enum {
  CSR_MISA_A      =  0, 
  CSR_MISA_B      =  1, 
  CSR_MISA_C      =  2, 
  CSR_MISA_D      =  3, 
  CSR_MISA_E      =  4, 
  CSR_MISA_F      =  5, 
  CSR_MISA_I      =  8, 
  CSR_MISA_M      = 12, 
  CSR_MISA_U      = 20, 
  CSR_MISA_X      = 23, 
  CSR_MISA_MXL_LO = 30, 
  CSR_MISA_MXL_HI = 31  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_XISA_enum {
  // ISA (sub-)extensions
  CSR_MXISA_ZICSR     =  0, 
  CSR_MXISA_ZIFENCEI  =  1, 
  CSR_MXISA_ZMMUL     =  2, 
  CSR_MXISA_ZXCFU     =  3, 
  CSR_MXISA_SMCNTRPMF =  4, 
  CSR_MXISA_ZFINX     =  5, 
  CSR_MXISA_ZICOND    =  6, 
  CSR_MXISA_ZICNTR    =  7, 
  CSR_MXISA_PMP       =  8, 
  CSR_MXISA_ZIHPM     =  9, 
  CSR_MXISA_SDEXT     = 10, 
  CSR_MXISA_SDTRIG    = 11, 
  // Misc
  CSR_MXISA_IS_SIM    = 20, 
  // Tuning options
  CSR_MXISA_RFHWRST   = 29, 
  CSR_MXISA_FASTMUL   = 30, 
  CSR_MXISA_FASTSHIFT = 31  
};
 
 
/**********************************************************************/
enum NEORV32_HPMCNT_EVENT_enum {
  HPMCNT_EVENT_CY      = 0,  
  HPMCNT_EVENT_IR      = 2,  
  HPMCNT_EVENT_CIR     = 3,  
  HPMCNT_EVENT_WAIT_IF = 4,  
  HPMCNT_EVENT_WAIT_II = 5,  
  HPMCNT_EVENT_WAIT_MC = 6,  
  HPMCNT_EVENT_LOAD    = 7,  
  HPMCNT_EVENT_STORE   = 8,  
  HPMCNT_EVENT_WAIT_LS = 9,  
  HPMCNT_EVENT_JUMP    = 10, 
  HPMCNT_EVENT_BRANCH  = 11, 
  HPMCNT_EVENT_TBRANCH = 12, 
  HPMCNT_EVENT_TRAP    = 13, 
  HPMCNT_EVENT_ILLEGAL = 14  
};
 
 
/**********************************************************************/
enum NEORV32_PMPCFG_ATTRIBUTES_enum {
  PMPCFG_R     = 0, 
  PMPCFG_W     = 1, 
  PMPCFG_X     = 2, 
  PMPCFG_A_LSB = 3, 
  PMPCFG_A_MSB = 4, 
  PMPCFG_L     = 7  
};
 
/**********************************************************************/
enum NEORV32_PMP_MODES_enum {
  PMP_OFF   = 0, 
  PMP_TOR   = 1, 
  PMP_NA4   = 2, 
  PMP_NAPOT = 3  
};
 
 
/**********************************************************************/
enum NEORV32_EXCEPTION_CODES_enum {
  TRAP_CODE_I_MISALIGNED = 0x00000000U, 
  TRAP_CODE_I_ACCESS     = 0x00000001U, 
  TRAP_CODE_I_ILLEGAL    = 0x00000002U, 
  TRAP_CODE_BREAKPOINT   = 0x00000003U, 
  TRAP_CODE_L_MISALIGNED = 0x00000004U, 
  TRAP_CODE_L_ACCESS     = 0x00000005U, 
  TRAP_CODE_S_MISALIGNED = 0x00000006U, 
  TRAP_CODE_S_ACCESS     = 0x00000007U, 
  TRAP_CODE_UENV_CALL    = 0x00000008U, 
  TRAP_CODE_MENV_CALL    = 0x0000000bU, 
  TRAP_CODE_MSI          = 0x80000003U, 
  TRAP_CODE_MTI          = 0x80000007U, 
  TRAP_CODE_MEI          = 0x8000000bU, 
  TRAP_CODE_FIRQ_0       = 0x80000010U, 
  TRAP_CODE_FIRQ_1       = 0x80000011U, 
  TRAP_CODE_FIRQ_2       = 0x80000012U, 
  TRAP_CODE_FIRQ_3       = 0x80000013U, 
  TRAP_CODE_FIRQ_4       = 0x80000014U, 
  TRAP_CODE_FIRQ_5       = 0x80000015U, 
  TRAP_CODE_FIRQ_6       = 0x80000016U, 
  TRAP_CODE_FIRQ_7       = 0x80000017U, 
  TRAP_CODE_FIRQ_8       = 0x80000018U, 
  TRAP_CODE_FIRQ_9       = 0x80000019U, 
  TRAP_CODE_FIRQ_10      = 0x8000001aU, 
  TRAP_CODE_FIRQ_11      = 0x8000001bU, 
  TRAP_CODE_FIRQ_12      = 0x8000001cU, 
  TRAP_CODE_FIRQ_13      = 0x8000001dU, 
  TRAP_CODE_FIRQ_14      = 0x8000001eU, 
  TRAP_CODE_FIRQ_15      = 0x8000001fU  
};
 
 
#endif // neorv32_cpu_csr_h