NEORV32 - Software Framework Documentation
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neorv32_cpu_csr.h
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1// #################################################################################################
2// # << NEORV32: neorv32_cpu_csr.h - Control and Status Registers Definitions >> #
3// # ********************************************************************************************* #
4// # BSD 3-Clause License #
5// # #
6// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
7// # #
8// # Redistribution and use in source and binary forms, with or without modification, are #
9// # permitted provided that the following conditions are met: #
10// # #
11// # 1. Redistributions of source code must retain the above copyright notice, this list of #
12// # conditions and the following disclaimer. #
13// # #
14// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
15// # conditions and the following disclaimer in the documentation and/or other materials #
16// # provided with the distribution. #
17// # #
18// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
19// # endorse or promote products derived from this software without specific prior written #
20// # permission. #
21// # #
22// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
23// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
24// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
25// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
26// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
28// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
29// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
30// # OF THE POSSIBILITY OF SUCH DAMAGE. #
31// # ********************************************************************************************* #
32// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
33// #################################################################################################
34
35
36/**********************************************************************/
41#ifndef neorv32_cpu_csr_h
42#define neorv32_cpu_csr_h
43
44
45/**********************************************************************/
49 /* floating-point unit control and status */
50 CSR_FFLAGS = 0x001,
51 CSR_FRM = 0x002,
52 CSR_FCSR = 0x003,
54 /* machine control and status */
55 CSR_MSTATUS = 0x300,
56 CSR_MISA = 0x301,
57 CSR_MIE = 0x304,
58 CSR_MTVEC = 0x305,
60 CSR_MSTATUSH = 0x310,
62 CSR_MCYCLECFG = 0x321,
65 /* machine configuration */
66 CSR_MENVCFG = 0x30a,
67 CSR_MENVCFGH = 0x31a,
69 /* hardware performance monitors - event configuration */
84 /* machine trap control */
85 CSR_MSCRATCH = 0x340,
86 CSR_MEPC = 0x341,
87 CSR_MCAUSE = 0x342,
88 CSR_MTVAL = 0x343,
89 CSR_MIP = 0x344,
90 CSR_MTINST = 0x34a,
92 /* physical memory protection */
93 CSR_PMPCFG0 = 0x3a0,
94 CSR_PMPCFG1 = 0x3a1,
95 CSR_PMPCFG2 = 0x3a2,
96 CSR_PMPCFG3 = 0x3a3,
98 CSR_PMPADDR0 = 0x3b0,
99 CSR_PMPADDR1 = 0x3b1,
100 CSR_PMPADDR2 = 0x3b2,
101 CSR_PMPADDR3 = 0x3b3,
102 CSR_PMPADDR4 = 0x3b4,
103 CSR_PMPADDR5 = 0x3b5,
104 CSR_PMPADDR6 = 0x3b6,
105 CSR_PMPADDR7 = 0x3b7,
106 CSR_PMPADDR8 = 0x3b8,
107 CSR_PMPADDR9 = 0x3b9,
115 /* machine control and status - continued */
119 /* on-chip debugger - hardware trigger module */
120 CSR_TSELECT = 0x7a0,
121 CSR_TDATA1 = 0x7a1,
122 CSR_TDATA2 = 0x7a2,
123 CSR_TINFO = 0x7a4,
125 /* CPU debug mode CSRs - not accessible by software running outside of debug mode */
126 CSR_DCSR = 0x7b0,
127 CSR_DPC = 0x7b1,
130 /* custom functions unit (CFU) registers */
131 CSR_CFUREG0 = 0x800,
132 CSR_CFUREG1 = 0x801,
133 CSR_CFUREG2 = 0x802,
134 CSR_CFUREG3 = 0x803,
136 /* machine counters and timers */
137 CSR_MCYCLE = 0xb00,
138 CSR_MINSTRET = 0xb02,
153 CSR_MCYCLEH = 0xb80,
169 /* user counters and timers */
170 CSR_CYCLE = 0xc00,
171 CSR_INSTRET = 0xc02,
186 CSR_CYCLEH = 0xc80,
187 CSR_INSTRETH = 0xc82,
202 /* machine information registers */
204 CSR_MARCHID = 0xf12,
205 CSR_MIMPID = 0xf13,
206 CSR_MHARTID = 0xf14,
208 CSR_MXISA = 0xfc0
210
211
212/**********************************************************************/
222
223
224/**********************************************************************/
235
236
237/**********************************************************************/
274
275
276/**********************************************************************/
283
284
285/**********************************************************************/
292
293
294/**********************************************************************/
320
321
322/**********************************************************************/
348
349
350/**********************************************************************/
367
368
369/**********************************************************************/
395
396
397/**********************************************************************/
419
420
421/**********************************************************************/
432
433/**********************************************************************/
442
443
444/**********************************************************************/
449 TRAP_CODE_I_ACCESS = 0x00000001U,
450 TRAP_CODE_I_ILLEGAL = 0x00000002U,
451 TRAP_CODE_BREAKPOINT = 0x00000003U,
453 TRAP_CODE_L_ACCESS = 0x00000005U,
455 TRAP_CODE_S_ACCESS = 0x00000007U,
456 TRAP_CODE_UENV_CALL = 0x00000008U,
457 TRAP_CODE_MENV_CALL = 0x0000000bU,
458 TRAP_CODE_MSI = 0x80000003U,
459 TRAP_CODE_MTI = 0x80000007U,
460 TRAP_CODE_MEI = 0x8000000bU,
461 TRAP_CODE_FIRQ_0 = 0x80000010U,
462 TRAP_CODE_FIRQ_1 = 0x80000011U,
463 TRAP_CODE_FIRQ_2 = 0x80000012U,
464 TRAP_CODE_FIRQ_3 = 0x80000013U,
465 TRAP_CODE_FIRQ_4 = 0x80000014U,
466 TRAP_CODE_FIRQ_5 = 0x80000015U,
467 TRAP_CODE_FIRQ_6 = 0x80000016U,
468 TRAP_CODE_FIRQ_7 = 0x80000017U,
469 TRAP_CODE_FIRQ_8 = 0x80000018U,
470 TRAP_CODE_FIRQ_9 = 0x80000019U,
471 TRAP_CODE_FIRQ_10 = 0x8000001aU,
472 TRAP_CODE_FIRQ_11 = 0x8000001bU,
473 TRAP_CODE_FIRQ_12 = 0x8000001cU,
474 TRAP_CODE_FIRQ_13 = 0x8000001dU,
475 TRAP_CODE_FIRQ_14 = 0x8000001eU,
476 TRAP_CODE_FIRQ_15 = 0x8000001fU
478
479
480#endif // neorv32_cpu_csr_h
NEORV32_CSR_MIE_enum
Definition neorv32_cpu_csr.h:297
@ CSR_MIE_FIRQ9E
Definition neorv32_cpu_csr.h:312
@ CSR_MIE_FIRQ13E
Definition neorv32_cpu_csr.h:316
@ CSR_MIE_FIRQ5E
Definition neorv32_cpu_csr.h:308
@ CSR_MIE_MTIE
Definition neorv32_cpu_csr.h:299
@ CSR_MIE_FIRQ8E
Definition neorv32_cpu_csr.h:311
@ CSR_MIE_FIRQ7E
Definition neorv32_cpu_csr.h:310
@ CSR_MIE_FIRQ12E
Definition neorv32_cpu_csr.h:315
@ CSR_MIE_FIRQ4E
Definition neorv32_cpu_csr.h:307
@ CSR_MIE_FIRQ3E
Definition neorv32_cpu_csr.h:306
@ CSR_MIE_FIRQ14E
Definition neorv32_cpu_csr.h:317
@ CSR_MIE_FIRQ6E
Definition neorv32_cpu_csr.h:309
@ CSR_MIE_FIRQ0E
Definition neorv32_cpu_csr.h:303
@ CSR_MIE_FIRQ15E
Definition neorv32_cpu_csr.h:318
@ CSR_MIE_FIRQ1E
Definition neorv32_cpu_csr.h:304
@ CSR_MIE_MEIE
Definition neorv32_cpu_csr.h:300
@ CSR_MIE_FIRQ11E
Definition neorv32_cpu_csr.h:314
@ CSR_MIE_FIRQ2E
Definition neorv32_cpu_csr.h:305
@ CSR_MIE_MSIE
Definition neorv32_cpu_csr.h:298
@ CSR_MIE_FIRQ10E
Definition neorv32_cpu_csr.h:313
NEORV32_HPMCNT_EVENT_enum
Definition neorv32_cpu_csr.h:400
@ HPMCNT_EVENT_LOAD
Definition neorv32_cpu_csr.h:408
@ HPMCNT_EVENT_CY
Definition neorv32_cpu_csr.h:401
@ HPMCNT_EVENT_TRAP
Definition neorv32_cpu_csr.h:416
@ HPMCNT_EVENT_STORE
Definition neorv32_cpu_csr.h:409
@ HPMCNT_EVENT_WAIT_LS
Definition neorv32_cpu_csr.h:410
@ HPMCNT_EVENT_WAIT_MC
Definition neorv32_cpu_csr.h:407
@ HPMCNT_EVENT_TBRANCH
Definition neorv32_cpu_csr.h:414
@ HPMCNT_EVENT_WAIT_IF
Definition neorv32_cpu_csr.h:405
@ HPMCNT_EVENT_BRANCH
Definition neorv32_cpu_csr.h:413
@ HPMCNT_EVENT_IR
Definition neorv32_cpu_csr.h:402
@ HPMCNT_EVENT_ILLEGAL
Definition neorv32_cpu_csr.h:417
@ HPMCNT_EVENT_JUMP
Definition neorv32_cpu_csr.h:412
@ HPMCNT_EVENT_CIR
Definition neorv32_cpu_csr.h:404
@ HPMCNT_EVENT_WAIT_II
Definition neorv32_cpu_csr.h:406
NEORV32_CSR_MIP_enum
Definition neorv32_cpu_csr.h:325
@ CSR_MIP_FIRQ12P
Definition neorv32_cpu_csr.h:343
@ CSR_MIP_FIRQ15P
Definition neorv32_cpu_csr.h:346
@ CSR_MIP_MSIP
Definition neorv32_cpu_csr.h:326
@ CSR_MIP_FIRQ13P
Definition neorv32_cpu_csr.h:344
@ CSR_MIP_MEIP
Definition neorv32_cpu_csr.h:328
@ CSR_MIP_FIRQ0P
Definition neorv32_cpu_csr.h:331
@ CSR_MIP_FIRQ10P
Definition neorv32_cpu_csr.h:341
@ CSR_MIP_FIRQ1P
Definition neorv32_cpu_csr.h:332
@ CSR_MIP_MTIP
Definition neorv32_cpu_csr.h:327
@ CSR_MIP_FIRQ11P
Definition neorv32_cpu_csr.h:342
@ CSR_MIP_FIRQ3P
Definition neorv32_cpu_csr.h:334
@ CSR_MIP_FIRQ5P
Definition neorv32_cpu_csr.h:336
@ CSR_MIP_FIRQ14P
Definition neorv32_cpu_csr.h:345
@ CSR_MIP_FIRQ7P
Definition neorv32_cpu_csr.h:338
@ CSR_MIP_FIRQ4P
Definition neorv32_cpu_csr.h:335
@ CSR_MIP_FIRQ9P
Definition neorv32_cpu_csr.h:340
@ CSR_MIP_FIRQ2P
Definition neorv32_cpu_csr.h:333
@ CSR_MIP_FIRQ8P
Definition neorv32_cpu_csr.h:339
@ CSR_MIP_FIRQ6P
Definition neorv32_cpu_csr.h:337
NEORV32_CSR_MINSTRETCFGH_enum
Definition neorv32_cpu_csr.h:288
@ CSR_MINSTRETCFGH_UINH
Definition neorv32_cpu_csr.h:289
@ CSR_MINSTRETCFGH_MINH
Definition neorv32_cpu_csr.h:290
NEORV32_CSR_MSTATUS_enum
Definition neorv32_cpu_csr.h:227
@ CSR_MSTATUS_MPRV
Definition neorv32_cpu_csr.h:232
@ CSR_MSTATUS_MPP_H
Definition neorv32_cpu_csr.h:231
@ CSR_MSTATUS_MPIE
Definition neorv32_cpu_csr.h:229
@ CSR_MSTATUS_TW
Definition neorv32_cpu_csr.h:233
@ CSR_MSTATUS_MIE
Definition neorv32_cpu_csr.h:228
@ CSR_MSTATUS_MPP_L
Definition neorv32_cpu_csr.h:230
NEORV32_PMP_MODES_enum
Definition neorv32_cpu_csr.h:436
@ PMP_OFF
Definition neorv32_cpu_csr.h:437
@ PMP_TOR
Definition neorv32_cpu_csr.h:438
@ PMP_NA4
Definition neorv32_cpu_csr.h:439
@ PMP_NAPOT
Definition neorv32_cpu_csr.h:440
NEORV32_CSR_MCYCLECFGH_enum
Definition neorv32_cpu_csr.h:279
@ CSR_MCYCLECFGH_UINH
Definition neorv32_cpu_csr.h:280
@ CSR_MCYCLECFGH_MINH
Definition neorv32_cpu_csr.h:281
NEORV32_CSR_MCOUNTINHIBIT_enum
Definition neorv32_cpu_csr.h:240
@ CSR_MCOUNTINHIBIT_HPM15
Definition neorv32_cpu_csr.h:256
@ CSR_MCOUNTINHIBIT_HPM9
Definition neorv32_cpu_csr.h:250
@ CSR_MCOUNTINHIBIT_HPM30
Definition neorv32_cpu_csr.h:271
@ CSR_MCOUNTINHIBIT_HPM26
Definition neorv32_cpu_csr.h:267
@ CSR_MCOUNTINHIBIT_HPM31
Definition neorv32_cpu_csr.h:272
@ CSR_MCOUNTINHIBIT_HPM21
Definition neorv32_cpu_csr.h:262
@ CSR_MCOUNTINHIBIT_CY
Definition neorv32_cpu_csr.h:241
@ CSR_MCOUNTINHIBIT_HPM5
Definition neorv32_cpu_csr.h:246
@ CSR_MCOUNTINHIBIT_HPM28
Definition neorv32_cpu_csr.h:269
@ CSR_MCOUNTINHIBIT_HPM19
Definition neorv32_cpu_csr.h:260
@ CSR_MCOUNTINHIBIT_HPM7
Definition neorv32_cpu_csr.h:248
@ CSR_MCOUNTINHIBIT_HPM4
Definition neorv32_cpu_csr.h:245
@ CSR_MCOUNTINHIBIT_HPM27
Definition neorv32_cpu_csr.h:268
@ CSR_MCOUNTINHIBIT_IR
Definition neorv32_cpu_csr.h:242
@ CSR_MCOUNTINHIBIT_HPM16
Definition neorv32_cpu_csr.h:257
@ CSR_MCOUNTINHIBIT_HPM24
Definition neorv32_cpu_csr.h:265
@ CSR_MCOUNTINHIBIT_HPM23
Definition neorv32_cpu_csr.h:264
@ CSR_MCOUNTINHIBIT_HPM17
Definition neorv32_cpu_csr.h:258
@ CSR_MCOUNTINHIBIT_HPM12
Definition neorv32_cpu_csr.h:253
@ CSR_MCOUNTINHIBIT_HPM10
Definition neorv32_cpu_csr.h:251
@ CSR_MCOUNTINHIBIT_HPM29
Definition neorv32_cpu_csr.h:270
@ CSR_MCOUNTINHIBIT_HPM18
Definition neorv32_cpu_csr.h:259
@ CSR_MCOUNTINHIBIT_HPM14
Definition neorv32_cpu_csr.h:255
@ CSR_MCOUNTINHIBIT_HPM8
Definition neorv32_cpu_csr.h:249
@ CSR_MCOUNTINHIBIT_HPM11
Definition neorv32_cpu_csr.h:252
@ CSR_MCOUNTINHIBIT_HPM6
Definition neorv32_cpu_csr.h:247
@ CSR_MCOUNTINHIBIT_HPM13
Definition neorv32_cpu_csr.h:254
@ CSR_MCOUNTINHIBIT_HPM20
Definition neorv32_cpu_csr.h:261
@ CSR_MCOUNTINHIBIT_HPM25
Definition neorv32_cpu_csr.h:266
@ CSR_MCOUNTINHIBIT_HPM22
Definition neorv32_cpu_csr.h:263
@ CSR_MCOUNTINHIBIT_HPM3
Definition neorv32_cpu_csr.h:244
NEORV32_PMPCFG_ATTRIBUTES_enum
Definition neorv32_cpu_csr.h:424
@ PMPCFG_L
Definition neorv32_cpu_csr.h:430
@ PMPCFG_A_MSB
Definition neorv32_cpu_csr.h:429
@ PMPCFG_W
Definition neorv32_cpu_csr.h:426
@ PMPCFG_A_LSB
Definition neorv32_cpu_csr.h:428
@ PMPCFG_R
Definition neorv32_cpu_csr.h:425
@ PMPCFG_X
Definition neorv32_cpu_csr.h:427
NEORV32_CSR_enum
Definition neorv32_cpu_csr.h:48
@ CSR_HPMCOUNTER14H
Definition neorv32_cpu_csr.h:199
@ CSR_MCONFIGPTR
Definition neorv32_cpu_csr.h:207
@ CSR_PMPCFG3
Definition neorv32_cpu_csr.h:96
@ CSR_MIMPID
Definition neorv32_cpu_csr.h:205
@ CSR_MHPMEVENT15
Definition neorv32_cpu_csr.h:82
@ CSR_MINSTRETCFGH
Definition neorv32_cpu_csr.h:117
@ CSR_PMPCFG2
Definition neorv32_cpu_csr.h:95
@ CSR_DSCRATCH0
Definition neorv32_cpu_csr.h:128
@ CSR_HPMCOUNTER15H
Definition neorv32_cpu_csr.h:200
@ CSR_HPMCOUNTER7
Definition neorv32_cpu_csr.h:176
@ CSR_MHPMCOUNTER12
Definition neorv32_cpu_csr.h:148
@ CSR_MCOUNTEREN
Definition neorv32_cpu_csr.h:59
@ CSR_MHPMCOUNTER9
Definition neorv32_cpu_csr.h:145
@ CSR_MHPMEVENT6
Definition neorv32_cpu_csr.h:73
@ CSR_MHPMCOUNTER10H
Definition neorv32_cpu_csr.h:162
@ CSR_MHPMCOUNTER15
Definition neorv32_cpu_csr.h:151
@ CSR_PMPCFG1
Definition neorv32_cpu_csr.h:94
@ CSR_PMPADDR12
Definition neorv32_cpu_csr.h:110
@ CSR_MHPMEVENT10
Definition neorv32_cpu_csr.h:77
@ CSR_HPMCOUNTER13
Definition neorv32_cpu_csr.h:182
@ CSR_MHPMEVENT5
Definition neorv32_cpu_csr.h:72
@ CSR_MHPMCOUNTER3H
Definition neorv32_cpu_csr.h:155
@ CSR_MCYCLECFGH
Definition neorv32_cpu_csr.h:116
@ CSR_MCYCLEH
Definition neorv32_cpu_csr.h:153
@ CSR_HPMCOUNTER11H
Definition neorv32_cpu_csr.h:196
@ CSR_MCAUSE
Definition neorv32_cpu_csr.h:87
@ CSR_MHPMEVENT7
Definition neorv32_cpu_csr.h:74
@ CSR_MHPMCOUNTER4H
Definition neorv32_cpu_csr.h:156
@ CSR_PMPADDR13
Definition neorv32_cpu_csr.h:111
@ CSR_MCYCLE
Definition neorv32_cpu_csr.h:137
@ CSR_MHPMCOUNTER12H
Definition neorv32_cpu_csr.h:164
@ CSR_CFUREG1
Definition neorv32_cpu_csr.h:132
@ CSR_MXISA
Definition neorv32_cpu_csr.h:208
@ CSR_MCOUNTINHIBIT
Definition neorv32_cpu_csr.h:61
@ CSR_PMPADDR11
Definition neorv32_cpu_csr.h:109
@ CSR_HPMCOUNTER3
Definition neorv32_cpu_csr.h:172
@ CSR_CFUREG2
Definition neorv32_cpu_csr.h:133
@ CSR_HPMCOUNTER6H
Definition neorv32_cpu_csr.h:191
@ CSR_MENVCFGH
Definition neorv32_cpu_csr.h:67
@ CSR_MHPMCOUNTER6H
Definition neorv32_cpu_csr.h:158
@ CSR_MHPMEVENT3
Definition neorv32_cpu_csr.h:70
@ CSR_MTINST
Definition neorv32_cpu_csr.h:90
@ CSR_HPMCOUNTER13H
Definition neorv32_cpu_csr.h:198
@ CSR_PMPADDR9
Definition neorv32_cpu_csr.h:107
@ CSR_MHPMCOUNTER10
Definition neorv32_cpu_csr.h:146
@ CSR_MHPMCOUNTER8
Definition neorv32_cpu_csr.h:144
@ CSR_MEPC
Definition neorv32_cpu_csr.h:86
@ CSR_MHPMCOUNTER13H
Definition neorv32_cpu_csr.h:165
@ CSR_FCSR
Definition neorv32_cpu_csr.h:52
@ CSR_FFLAGS
Definition neorv32_cpu_csr.h:50
@ CSR_HPMCOUNTER7H
Definition neorv32_cpu_csr.h:192
@ CSR_PMPADDR15
Definition neorv32_cpu_csr.h:113
@ CSR_PMPADDR1
Definition neorv32_cpu_csr.h:99
@ CSR_MHARTID
Definition neorv32_cpu_csr.h:206
@ CSR_DCSR
Definition neorv32_cpu_csr.h:126
@ CSR_HPMCOUNTER15
Definition neorv32_cpu_csr.h:184
@ CSR_MHPMCOUNTER9H
Definition neorv32_cpu_csr.h:161
@ CSR_HPMCOUNTER12H
Definition neorv32_cpu_csr.h:197
@ CSR_MHPMCOUNTER5H
Definition neorv32_cpu_csr.h:157
@ CSR_MTVAL
Definition neorv32_cpu_csr.h:88
@ CSR_FRM
Definition neorv32_cpu_csr.h:51
@ CSR_MHPMEVENT11
Definition neorv32_cpu_csr.h:78
@ CSR_MHPMCOUNTER11H
Definition neorv32_cpu_csr.h:163
@ CSR_TDATA1
Definition neorv32_cpu_csr.h:121
@ CSR_INSTRET
Definition neorv32_cpu_csr.h:171
@ CSR_HPMCOUNTER4H
Definition neorv32_cpu_csr.h:189
@ CSR_MHPMCOUNTER11
Definition neorv32_cpu_csr.h:147
@ CSR_PMPADDR0
Definition neorv32_cpu_csr.h:98
@ CSR_PMPADDR3
Definition neorv32_cpu_csr.h:101
@ CSR_MHPMEVENT13
Definition neorv32_cpu_csr.h:80
@ CSR_MHPMCOUNTER7
Definition neorv32_cpu_csr.h:143
@ CSR_PMPADDR14
Definition neorv32_cpu_csr.h:112
@ CSR_MHPMEVENT14
Definition neorv32_cpu_csr.h:81
@ CSR_HPMCOUNTER4
Definition neorv32_cpu_csr.h:173
@ CSR_MINSTRET
Definition neorv32_cpu_csr.h:138
@ CSR_INSTRETH
Definition neorv32_cpu_csr.h:187
@ CSR_MHPMCOUNTER4
Definition neorv32_cpu_csr.h:140
@ CSR_MHPMCOUNTER13
Definition neorv32_cpu_csr.h:149
@ CSR_MENVCFG
Definition neorv32_cpu_csr.h:66
@ CSR_MHPMCOUNTER8H
Definition neorv32_cpu_csr.h:160
@ CSR_HPMCOUNTER11
Definition neorv32_cpu_csr.h:180
@ CSR_PMPADDR2
Definition neorv32_cpu_csr.h:100
@ CSR_CYCLEH
Definition neorv32_cpu_csr.h:186
@ CSR_HPMCOUNTER6
Definition neorv32_cpu_csr.h:175
@ CSR_HPMCOUNTER10
Definition neorv32_cpu_csr.h:179
@ CSR_HPMCOUNTER14
Definition neorv32_cpu_csr.h:183
@ CSR_MTVEC
Definition neorv32_cpu_csr.h:58
@ CSR_HPMCOUNTER8H
Definition neorv32_cpu_csr.h:193
@ CSR_HPMCOUNTER3H
Definition neorv32_cpu_csr.h:188
@ CSR_TSELECT
Definition neorv32_cpu_csr.h:120
@ CSR_CYCLE
Definition neorv32_cpu_csr.h:170
@ CSR_HPMCOUNTER5
Definition neorv32_cpu_csr.h:174
@ CSR_HPMCOUNTER9
Definition neorv32_cpu_csr.h:178
@ CSR_MHPMEVENT4
Definition neorv32_cpu_csr.h:71
@ CSR_MCYCLECFG
Definition neorv32_cpu_csr.h:62
@ CSR_MHPMCOUNTER7H
Definition neorv32_cpu_csr.h:159
@ CSR_MSTATUSH
Definition neorv32_cpu_csr.h:60
@ CSR_MHPMCOUNTER14H
Definition neorv32_cpu_csr.h:166
@ CSR_HPMCOUNTER8
Definition neorv32_cpu_csr.h:177
@ CSR_MIE
Definition neorv32_cpu_csr.h:57
@ CSR_HPMCOUNTER9H
Definition neorv32_cpu_csr.h:194
@ CSR_PMPADDR4
Definition neorv32_cpu_csr.h:102
@ CSR_TDATA2
Definition neorv32_cpu_csr.h:122
@ CSR_MSTATUS
Definition neorv32_cpu_csr.h:55
@ CSR_HPMCOUNTER5H
Definition neorv32_cpu_csr.h:190
@ CSR_MHPMEVENT8
Definition neorv32_cpu_csr.h:75
@ CSR_MHPMEVENT12
Definition neorv32_cpu_csr.h:79
@ CSR_MARCHID
Definition neorv32_cpu_csr.h:204
@ CSR_PMPADDR10
Definition neorv32_cpu_csr.h:108
@ CSR_PMPADDR5
Definition neorv32_cpu_csr.h:103
@ CSR_MHPMCOUNTER14
Definition neorv32_cpu_csr.h:150
@ CSR_MIP
Definition neorv32_cpu_csr.h:89
@ CSR_MISA
Definition neorv32_cpu_csr.h:56
@ CSR_MHPMCOUNTER3
Definition neorv32_cpu_csr.h:139
@ CSR_CFUREG0
Definition neorv32_cpu_csr.h:131
@ CSR_MSCRATCH
Definition neorv32_cpu_csr.h:85
@ CSR_HPMCOUNTER10H
Definition neorv32_cpu_csr.h:195
@ CSR_HPMCOUNTER12
Definition neorv32_cpu_csr.h:181
@ CSR_MINSTRETCFG
Definition neorv32_cpu_csr.h:63
@ CSR_PMPADDR7
Definition neorv32_cpu_csr.h:105
@ CSR_PMPADDR8
Definition neorv32_cpu_csr.h:106
@ CSR_CFUREG3
Definition neorv32_cpu_csr.h:134
@ CSR_MHPMCOUNTER5
Definition neorv32_cpu_csr.h:141
@ CSR_PMPCFG0
Definition neorv32_cpu_csr.h:93
@ CSR_DPC
Definition neorv32_cpu_csr.h:127
@ CSR_PMPADDR6
Definition neorv32_cpu_csr.h:104
@ CSR_MVENDORID
Definition neorv32_cpu_csr.h:203
@ CSR_MHPMCOUNTER15H
Definition neorv32_cpu_csr.h:167
@ CSR_MHPMCOUNTER6
Definition neorv32_cpu_csr.h:142
@ CSR_MHPMEVENT9
Definition neorv32_cpu_csr.h:76
@ CSR_TINFO
Definition neorv32_cpu_csr.h:123
@ CSR_MINSTRETH
Definition neorv32_cpu_csr.h:154
NEORV32_EXCEPTION_CODES_enum
Definition neorv32_cpu_csr.h:447
@ TRAP_CODE_I_MISALIGNED
Definition neorv32_cpu_csr.h:448
@ TRAP_CODE_FIRQ_0
Definition neorv32_cpu_csr.h:461
@ TRAP_CODE_FIRQ_12
Definition neorv32_cpu_csr.h:473
@ TRAP_CODE_MTI
Definition neorv32_cpu_csr.h:459
@ TRAP_CODE_S_MISALIGNED
Definition neorv32_cpu_csr.h:454
@ TRAP_CODE_MEI
Definition neorv32_cpu_csr.h:460
@ TRAP_CODE_MENV_CALL
Definition neorv32_cpu_csr.h:457
@ TRAP_CODE_L_ACCESS
Definition neorv32_cpu_csr.h:453
@ TRAP_CODE_BREAKPOINT
Definition neorv32_cpu_csr.h:451
@ TRAP_CODE_FIRQ_9
Definition neorv32_cpu_csr.h:470
@ TRAP_CODE_FIRQ_3
Definition neorv32_cpu_csr.h:464
@ TRAP_CODE_FIRQ_10
Definition neorv32_cpu_csr.h:471
@ TRAP_CODE_FIRQ_5
Definition neorv32_cpu_csr.h:466
@ TRAP_CODE_L_MISALIGNED
Definition neorv32_cpu_csr.h:452
@ TRAP_CODE_I_ACCESS
Definition neorv32_cpu_csr.h:449
@ TRAP_CODE_S_ACCESS
Definition neorv32_cpu_csr.h:455
@ TRAP_CODE_FIRQ_13
Definition neorv32_cpu_csr.h:474
@ TRAP_CODE_FIRQ_6
Definition neorv32_cpu_csr.h:467
@ TRAP_CODE_FIRQ_14
Definition neorv32_cpu_csr.h:475
@ TRAP_CODE_FIRQ_11
Definition neorv32_cpu_csr.h:472
@ TRAP_CODE_UENV_CALL
Definition neorv32_cpu_csr.h:456
@ TRAP_CODE_FIRQ_15
Definition neorv32_cpu_csr.h:476
@ TRAP_CODE_FIRQ_4
Definition neorv32_cpu_csr.h:465
@ TRAP_CODE_FIRQ_8
Definition neorv32_cpu_csr.h:469
@ TRAP_CODE_FIRQ_2
Definition neorv32_cpu_csr.h:463
@ TRAP_CODE_FIRQ_1
Definition neorv32_cpu_csr.h:462
@ TRAP_CODE_MSI
Definition neorv32_cpu_csr.h:458
@ TRAP_CODE_FIRQ_7
Definition neorv32_cpu_csr.h:468
@ TRAP_CODE_I_ILLEGAL
Definition neorv32_cpu_csr.h:450
NEORV32_CSR_XISA_enum
Definition neorv32_cpu_csr.h:372
@ CSR_MXISA_ZICNTR
Definition neorv32_cpu_csr.h:381
@ CSR_MXISA_FASTMUL
Definition neorv32_cpu_csr.h:392
@ CSR_MXISA_SMCNTRPMF
Definition neorv32_cpu_csr.h:378
@ CSR_MXISA_ZFINX
Definition neorv32_cpu_csr.h:379
@ CSR_MXISA_SDTRIG
Definition neorv32_cpu_csr.h:385
@ CSR_MXISA_RFHWRST
Definition neorv32_cpu_csr.h:391
@ CSR_MXISA_ZIFENCEI
Definition neorv32_cpu_csr.h:375
@ CSR_MXISA_ZMMUL
Definition neorv32_cpu_csr.h:376
@ CSR_MXISA_IS_SIM
Definition neorv32_cpu_csr.h:388
@ CSR_MXISA_ZICOND
Definition neorv32_cpu_csr.h:380
@ CSR_MXISA_SDEXT
Definition neorv32_cpu_csr.h:384
@ CSR_MXISA_ZIHPM
Definition neorv32_cpu_csr.h:383
@ CSR_MXISA_PMP
Definition neorv32_cpu_csr.h:382
@ CSR_MXISA_ZICSR
Definition neorv32_cpu_csr.h:374
@ CSR_MXISA_FASTSHIFT
Definition neorv32_cpu_csr.h:393
@ CSR_MXISA_ZXCFU
Definition neorv32_cpu_csr.h:377
NEORV32_CSR_FFLAGS_enum
Definition neorv32_cpu_csr.h:215
@ CSR_FFLAGS_DZ
Definition neorv32_cpu_csr.h:219
@ CSR_FFLAGS_NV
Definition neorv32_cpu_csr.h:220
@ CSR_FFLAGS_OF
Definition neorv32_cpu_csr.h:218
@ CSR_FFLAGS_NX
Definition neorv32_cpu_csr.h:216
@ CSR_FFLAGS_UF
Definition neorv32_cpu_csr.h:217
NEORV32_CSR_MISA_enum
Definition neorv32_cpu_csr.h:353
@ CSR_MISA_E
Definition neorv32_cpu_csr.h:358
@ CSR_MISA_X
Definition neorv32_cpu_csr.h:363
@ CSR_MISA_D
Definition neorv32_cpu_csr.h:357
@ CSR_MISA_M
Definition neorv32_cpu_csr.h:361
@ CSR_MISA_I
Definition neorv32_cpu_csr.h:360
@ CSR_MISA_C
Definition neorv32_cpu_csr.h:356
@ CSR_MISA_A
Definition neorv32_cpu_csr.h:354
@ CSR_MISA_F
Definition neorv32_cpu_csr.h:359
@ CSR_MISA_MXL_LO
Definition neorv32_cpu_csr.h:364
@ CSR_MISA_U
Definition neorv32_cpu_csr.h:362
@ CSR_MISA_B
Definition neorv32_cpu_csr.h:355
@ CSR_MISA_MXL_HI
Definition neorv32_cpu_csr.h:365