NEORV32 - Software Framework Documentation
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Helper functions and macros for custom "intrinsics" / instructions. More...
Go to the source code of this file.
Macros | |
R2-type instruction format, RISC-V-standard | |
#define | CUSTOM_INSTR_R2_TYPE(funct7, funct5, rs1, funct3, opcode) |
R3-type instruction format, RISC-V-standard | |
#define | CUSTOM_INSTR_R3_TYPE(funct7, rs2, rs1, funct3, opcode) |
R4-type instruction format, RISC-V-standard | |
#define | CUSTOM_INSTR_R4_TYPE(rs3, rs2, rs1, funct3, opcode) |
R5-type instruction format | |
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#define | CUSTOM_INSTR_R5_TYPE(rs4, rs3, rs2, rs1, opcode) |
I-type instruction format, RISC-V-standard | |
#define | CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) |
S-type instruction format, RISC-V-standard | |
#define | CUSTOM_INSTR_S_TYPE(imm12, rs2, rs1, funct3, opcode) |
Functions | |
Custom Instruction Intrinsics | |
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asm (".set regnum_x0 , 0") | |
asm (".set regnum_x1 , 1") | |
asm (".set regnum_x2 , 2") | |
asm (".set regnum_x3 , 3") | |
asm (".set regnum_x4 , 4") | |
asm (".set regnum_x5 , 5") | |
asm (".set regnum_x6 , 6") | |
asm (".set regnum_x7 , 7") | |
asm (".set regnum_x8 , 8") | |
asm (".set regnum_x9 , 9") | |
asm (".set regnum_x10 , 10") | |
asm (".set regnum_x11 , 11") | |
asm (".set regnum_x12 , 12") | |
asm (".set regnum_x13 , 13") | |
asm (".set regnum_x14 , 14") | |
asm (".set regnum_x15 , 15") | |
asm (".set regnum_x16 , 16") | |
asm (".set regnum_x17 , 17") | |
asm (".set regnum_x18 , 18") | |
asm (".set regnum_x19 , 19") | |
asm (".set regnum_x20 , 20") | |
asm (".set regnum_x21 , 21") | |
asm (".set regnum_x22 , 22") | |
asm (".set regnum_x23 , 23") | |
asm (".set regnum_x24 , 24") | |
asm (".set regnum_x25 , 25") | |
asm (".set regnum_x26 , 26") | |
asm (".set regnum_x27 , 27") | |
asm (".set regnum_x28 , 28") | |
asm (".set regnum_x29 , 29") | |
asm (".set regnum_x30 , 30") | |
asm (".set regnum_x31 , 31") | |
asm (".set RISCV_OPCODE_CUSTOM0 , 0b0001011") | |
asm (".set RISCV_OPCODE_CUSTOM1 , 0b0101011") | |
asm (".set RISCV_OPCODE_CUSTOM2 , 0b1011011") | |
asm (".set RISCV_OPCODE_CUSTOM3 , 0b1111011") | |
Helper functions and macros for custom "intrinsics" / instructions.
#define CUSTOM_INSTR_I_TYPE | ( | imm12, | |
rs1, | |||
funct3, | |||
opcode ) |
#define CUSTOM_INSTR_R2_TYPE | ( | funct7, | |
funct5, | |||
rs1, | |||
funct3, | |||
opcode ) |
#define CUSTOM_INSTR_R3_TYPE | ( | funct7, | |
rs2, | |||
rs1, | |||
funct3, | |||
opcode ) |
#define CUSTOM_INSTR_R4_TYPE | ( | rs3, | |
rs2, | |||
rs1, | |||
funct3, | |||
opcode ) |
#define CUSTOM_INSTR_R5_TYPE | ( | rs4, | |
rs3, | |||
rs2, | |||
rs1, | |||
opcode ) |
#define CUSTOM_INSTR_S_TYPE | ( | imm12, | |
rs2, | |||
rs1, | |||
funct3, | |||
opcode ) |
asm | ( | ".set | regnum_x0, |
0" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x1, |
1" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x10, |
10" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x11, |
11" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x12, |
12" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x13, |
13" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x14, |
14" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x15, |
15" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x16, |
16" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x17, |
17" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x18, |
18" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x19, |
19" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x2, |
2" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x20, |
20" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x21, |
21" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x22, |
22" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x23, |
23" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x24, |
24" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x25, |
25" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x26, |
26" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x27, |
27" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x28, |
28" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x29, |
29" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x3, |
3" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x30, |
30" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x31, |
31" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x4, |
4" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x5, |
5" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x6, |
6" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x7, |
7" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x8, |
8" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | regnum_x9, |
9" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | RISCV_OPCODE_CUSTOM0, |
0b0001011" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | RISCV_OPCODE_CUSTOM1, |
0b0101011" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | RISCV_OPCODE_CUSTOM2, |
0b1011011" | ) |
Official RISC-V opcodes for custom ISA extensions
asm | ( | ".set | RISCV_OPCODE_CUSTOM3, |
0b1111011" | ) |
Official RISC-V opcodes for custom ISA extensions