NEORV32 - Software Framework Documentation
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neorv32_intrinsics.h File Reference

Helper functions and macros for custom "intrinsics" / instructions. More...

Go to the source code of this file.

Macros

Custom instruction R1-type format
#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, opcode)
 
Custom instruction R2-type format
#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, opcode)
 
Custom instruction R3-type format
#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, opcode)
 
Custom instruction I-type format
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode)
 

Functions

Custom Instruction Intrinsics
 asm (".set regnum_x0 , 0")
 
 asm (".set regnum_x1 , 1")
 
 asm (".set regnum_x2 , 2")
 
 asm (".set regnum_x3 , 3")
 
 asm (".set regnum_x4 , 4")
 
 asm (".set regnum_x5 , 5")
 
 asm (".set regnum_x6 , 6")
 
 asm (".set regnum_x7 , 7")
 
 asm (".set regnum_x8 , 8")
 
 asm (".set regnum_x9 , 9")
 
 asm (".set regnum_x10 , 10")
 
 asm (".set regnum_x11 , 11")
 
 asm (".set regnum_x12 , 12")
 
 asm (".set regnum_x13 , 13")
 
 asm (".set regnum_x14 , 14")
 
 asm (".set regnum_x15 , 15")
 
 asm (".set regnum_x16 , 16")
 
 asm (".set regnum_x17 , 17")
 
 asm (".set regnum_x18 , 18")
 
 asm (".set regnum_x19 , 19")
 
 asm (".set regnum_x20 , 20")
 
 asm (".set regnum_x21 , 21")
 
 asm (".set regnum_x22 , 22")
 
 asm (".set regnum_x23 , 23")
 
 asm (".set regnum_x24 , 24")
 
 asm (".set regnum_x25 , 25")
 
 asm (".set regnum_x26 , 26")
 
 asm (".set regnum_x27 , 27")
 
 asm (".set regnum_x28 , 28")
 
 asm (".set regnum_x29 , 29")
 
 asm (".set regnum_x30 , 30")
 
 asm (".set regnum_x31 , 31")
 
 asm (".set RISCV_OPCODE_CUSTOM0 , 0b0001011")
 
 asm (".set RISCV_OPCODE_CUSTOM1 , 0b0101011")
 

Detailed Description

Helper functions and macros for custom "intrinsics" / instructions.

Macro Definition Documentation

◆ CUSTOM_INSTR_I_TYPE

#define CUSTOM_INSTR_I_TYPE (   imm12,
  rs1,
  funct3,
  opcode 
)
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1) \
); \
asm volatile ( \
".word ( \ (((" #imm12 ") & 0xfff) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1) \
); \
__return; \
})

◆ CUSTOM_INSTR_R1_TYPE

#define CUSTOM_INSTR_R1_TYPE (   funct7,
  funct5,
  rs1,
  funct3,
  opcode 
)
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1) \
); \
asm volatile( \
".word ( \ (((" #funct7 ") & 0x7f) << 25) | \ (((" #funct5 ") & 0x1f) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1) \
); \
__return; \
})

◆ CUSTOM_INSTR_R2_TYPE

#define CUSTOM_INSTR_R2_TYPE (   funct7,
  rs2,
  rs1,
  funct3,
  opcode 
)
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), \
[input_j] "r" (rs2) \
); \
asm volatile ( \
".word ( \ (((" #funct7 ") & 0x7f) << 25) | \ ((( regnum_%2 ) & 0x1f) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1), \
"r" (rs2) \
); \
__return; \
})

◆ CUSTOM_INSTR_R3_TYPE

#define CUSTOM_INSTR_R3_TYPE (   rs3,
  rs2,
  rs1,
  funct3,
  opcode 
)
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), \
[input_j] "r" (rs2), \
[input_k] "r" (rs3) \
); \
asm volatile ( \
".word ( \ ((( regnum_%3 ) & 0x1f) << 25) | \ ((( regnum_%2 ) & 0x1f) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1), \
"r" (rs2), \
"r" (rs3) \
); \
__return; \
})

Function Documentation

◆ asm() [1/34]

asm ( ".set  regnum_x0,
0"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [2/34]

asm ( ".set  regnum_x1,
1"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [3/34]

asm ( ".set  regnum_x10,
10"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [4/34]

asm ( ".set  regnum_x11,
11"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [5/34]

asm ( ".set  regnum_x12,
12"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [6/34]

asm ( ".set  regnum_x13,
13"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [7/34]

asm ( ".set  regnum_x14,
14"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [8/34]

asm ( ".set  regnum_x15,
15"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [9/34]

asm ( ".set  regnum_x16,
16"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [10/34]

asm ( ".set  regnum_x17,
17"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [11/34]

asm ( ".set  regnum_x18,
18"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [12/34]

asm ( ".set  regnum_x19,
19"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [13/34]

asm ( ".set  regnum_x2,
2"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [14/34]

asm ( ".set  regnum_x20,
20"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [15/34]

asm ( ".set  regnum_x21,
21"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [16/34]

asm ( ".set  regnum_x22,
22"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [17/34]

asm ( ".set  regnum_x23,
23"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [18/34]

asm ( ".set  regnum_x24,
24"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [19/34]

asm ( ".set  regnum_x25,
25"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [20/34]

asm ( ".set  regnum_x26,
26"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [21/34]

asm ( ".set  regnum_x27,
27"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [22/34]

asm ( ".set  regnum_x28,
28"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [23/34]

asm ( ".set  regnum_x29,
29"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [24/34]

asm ( ".set  regnum_x3,
3"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [25/34]

asm ( ".set  regnum_x30,
30"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [26/34]

asm ( ".set  regnum_x31,
31"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [27/34]

asm ( ".set  regnum_x4,
4"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [28/34]

asm ( ".set  regnum_x5,
5"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [29/34]

asm ( ".set  regnum_x6,
6"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [30/34]

asm ( ".set  regnum_x7,
7"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [31/34]

asm ( ".set  regnum_x8,
8"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [32/34]

asm ( ".set  regnum_x9,
9"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [33/34]

asm ( ".set  RISCV_OPCODE_CUSTOM0,
0b0001011"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)

◆ asm() [34/34]

asm ( ".set  RISCV_OPCODE_CUSTOM1,
0b0101011"   
)

Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1)