NEORV32 - Software Framework Documentation
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neorv32_intrinsics.h File Reference

Helper functions and macros for custom "intrinsics" / instructions. More...

Go to the source code of this file.

Macros

R2-type instruction format, RISC-V-standard
#define CUSTOM_INSTR_R2_TYPE(funct7, funct5, rs1, funct3, opcode)
 
R3-type instruction format, RISC-V-standard
#define CUSTOM_INSTR_R3_TYPE(funct7, rs2, rs1, funct3, opcode)
 
R4-type instruction format, RISC-V-standard
#define CUSTOM_INSTR_R4_TYPE(rs3, rs2, rs1, funct3, opcode)
 
R5-type instruction format
Warning
NOT RISC-V-standard, NEORV32-specific!
#define CUSTOM_INSTR_R5_TYPE(rs4, rs3, rs2, rs1, opcode)
 
I-type instruction format, RISC-V-standard
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode)
 
S-type instruction format, RISC-V-standard
#define CUSTOM_INSTR_S_TYPE(imm12, rs2, rs1, funct3, opcode)
 

Functions

Custom Instruction Intrinsics
 asm (".set regnum_x0 , 0")
 
 asm (".set regnum_x1 , 1")
 
 asm (".set regnum_x2 , 2")
 
 asm (".set regnum_x3 , 3")
 
 asm (".set regnum_x4 , 4")
 
 asm (".set regnum_x5 , 5")
 
 asm (".set regnum_x6 , 6")
 
 asm (".set regnum_x7 , 7")
 
 asm (".set regnum_x8 , 8")
 
 asm (".set regnum_x9 , 9")
 
 asm (".set regnum_x10 , 10")
 
 asm (".set regnum_x11 , 11")
 
 asm (".set regnum_x12 , 12")
 
 asm (".set regnum_x13 , 13")
 
 asm (".set regnum_x14 , 14")
 
 asm (".set regnum_x15 , 15")
 
 asm (".set regnum_x16 , 16")
 
 asm (".set regnum_x17 , 17")
 
 asm (".set regnum_x18 , 18")
 
 asm (".set regnum_x19 , 19")
 
 asm (".set regnum_x20 , 20")
 
 asm (".set regnum_x21 , 21")
 
 asm (".set regnum_x22 , 22")
 
 asm (".set regnum_x23 , 23")
 
 asm (".set regnum_x24 , 24")
 
 asm (".set regnum_x25 , 25")
 
 asm (".set regnum_x26 , 26")
 
 asm (".set regnum_x27 , 27")
 
 asm (".set regnum_x28 , 28")
 
 asm (".set regnum_x29 , 29")
 
 asm (".set regnum_x30 , 30")
 
 asm (".set regnum_x31 , 31")
 
 asm (".set RISCV_OPCODE_CUSTOM0 , 0b0001011")
 
 asm (".set RISCV_OPCODE_CUSTOM1 , 0b0101011")
 
 asm (".set RISCV_OPCODE_CUSTOM2 , 0b1011011")
 
 asm (".set RISCV_OPCODE_CUSTOM3 , 0b1111011")
 

Detailed Description

Helper functions and macros for custom "intrinsics" / instructions.

Macro Definition Documentation

◆ CUSTOM_INSTR_I_TYPE

#define CUSTOM_INSTR_I_TYPE ( imm12,
rs1,
funct3,
opcode )
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1) \
); \
asm volatile ( \
".word ( \ (((" #imm12 ") & 0xfff) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1) \
); \
__return; \
})

◆ CUSTOM_INSTR_R2_TYPE

#define CUSTOM_INSTR_R2_TYPE ( funct7,
funct5,
rs1,
funct3,
opcode )
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1) \
); \
asm volatile( \
".word ( \ (((" #funct7 ") & 0x7f) << 25) | \ (((" #funct5 ") & 0x1f) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1) \
); \
__return; \
})

◆ CUSTOM_INSTR_R3_TYPE

#define CUSTOM_INSTR_R3_TYPE ( funct7,
rs2,
rs1,
funct3,
opcode )
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), \
[input_j] "r" (rs2) \
); \
asm volatile ( \
".word ( \ (((" #funct7 ") & 0x7f) << 25) | \ ((( regnum_%2 ) & 0x1f) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1), \
"r" (rs2) \
); \
__return; \
})

◆ CUSTOM_INSTR_R4_TYPE

#define CUSTOM_INSTR_R4_TYPE ( rs3,
rs2,
rs1,
funct3,
opcode )
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), \
[input_j] "r" (rs2), \
[input_k] "r" (rs3) \
); \
asm volatile ( \
".word ( \ ((( regnum_%3 ) & 0x1f) << 27) | \ ((( regnum_%2 ) & 0x1f) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1), \
"r" (rs2), \
"r" (rs3) \
); \
__return; \
})

◆ CUSTOM_INSTR_R5_TYPE

#define CUSTOM_INSTR_R5_TYPE ( rs4,
rs3,
rs2,
rs1,
opcode )
Value:
({ \
uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), \
[input_j] "r" (rs2), \
[input_k] "r" (rs3), \
[input_l] "r" (rs4) \
); \
asm volatile ( \
".word ( \ ((( regnum_%3 ) & 0x1f) << 27) | \ (((( regnum_%4 ) >> 3) & 0x03) << 25) | \ ((( regnum_%2 ) & 0x1f) << 20) | \ ((( regnum_%1 ) & 0x1f) << 15) | \ ((( regnum_%4 ) & 0x07) << 12) | \ ((( regnum_%0 ) & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: [rd] "=r" (__return) \
: "r" (rs1), \
"r" (rs2), \
"r" (rs3), \
"r" (rs4) \
); \
__return; \
})

◆ CUSTOM_INSTR_S_TYPE

#define CUSTOM_INSTR_S_TYPE ( imm12,
rs2,
rs1,
funct3,
opcode )
Value:
({ \
asm volatile ( \
"" \
: \
: [input_i] "r" (rs1), \
[input_j] "r" (rs2) \
); \
asm volatile ( \
".word ( \ ((((" #imm12 ") >> 5) & 0x7f) << 25) | \ ((( regnum_%1 ) & 0x1f) << 20) | \ ((( regnum_%0 ) & 0x1f) << 15) | \ (((" #funct3 ") & 0x07) << 12) | \ (((" #imm12 ") & 0x1f) << 7) | \ (((" #opcode ") & 0x7f) << 0) \ );" \
: \
: "r" (rs1), \
"r" (rs2) \
); \
})

Function Documentation

◆ asm() [1/36]

asm ( ".set regnum_x0,
0"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [2/36]

asm ( ".set regnum_x1,
1"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [3/36]

asm ( ".set regnum_x10,
10"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [4/36]

asm ( ".set regnum_x11,
11"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [5/36]

asm ( ".set regnum_x12,
12"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [6/36]

asm ( ".set regnum_x13,
13"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [7/36]

asm ( ".set regnum_x14,
14"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [8/36]

asm ( ".set regnum_x15,
15"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [9/36]

asm ( ".set regnum_x16,
16"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [10/36]

asm ( ".set regnum_x17,
17"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [11/36]

asm ( ".set regnum_x18,
18"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [12/36]

asm ( ".set regnum_x19,
19"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [13/36]

asm ( ".set regnum_x2,
2"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [14/36]

asm ( ".set regnum_x20,
20"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [15/36]

asm ( ".set regnum_x21,
21"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [16/36]

asm ( ".set regnum_x22,
22"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [17/36]

asm ( ".set regnum_x23,
23"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [18/36]

asm ( ".set regnum_x24,
24"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [19/36]

asm ( ".set regnum_x25,
25"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [20/36]

asm ( ".set regnum_x26,
26"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [21/36]

asm ( ".set regnum_x27,
27"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [22/36]

asm ( ".set regnum_x28,
28"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [23/36]

asm ( ".set regnum_x29,
29"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [24/36]

asm ( ".set regnum_x3,
3"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [25/36]

asm ( ".set regnum_x30,
30"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [26/36]

asm ( ".set regnum_x31,
31"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [27/36]

asm ( ".set regnum_x4,
4"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [28/36]

asm ( ".set regnum_x5,
5"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [29/36]

asm ( ".set regnum_x6,
6"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [30/36]

asm ( ".set regnum_x7,
7"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [31/36]

asm ( ".set regnum_x8,
8"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [32/36]

asm ( ".set regnum_x9,
9"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [33/36]

asm ( ".set RISCV_OPCODE_CUSTOM0,
0b0001011"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [34/36]

asm ( ".set RISCV_OPCODE_CUSTOM1,
0b0101011"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [35/36]

asm ( ".set RISCV_OPCODE_CUSTOM2,
0b1011011"  )

Official RISC-V opcodes for custom ISA extensions

◆ asm() [36/36]

asm ( ".set RISCV_OPCODE_CUSTOM3,
0b1111011"  )

Official RISC-V opcodes for custom ISA extensions