NEORV32 Software Framework Documentation
The NEORV32 RISC-V Processor
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sw
lib
include
neorv32_intrinsics.h
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// ================================================================================ //
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// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
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// Copyright (c) NEORV32 contributors. //
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// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
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// Licensed under the BSD-3-Clause license, see LICENSE for details. //
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// SPDX-License-Identifier: BSD-3-Clause //
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// ================================================================================ //
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#ifndef NEORV32_INTRINSICS_H
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#define NEORV32_INTRINSICS_H
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#include <stdint.h>
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/**********************************************************************/
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asm
(
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".set reg_x0, 0 \n"
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".set reg_x1, 1 \n"
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".set reg_x2, 2 \n"
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".set reg_x3, 3 \n"
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".set reg_x4, 4 \n"
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".set reg_x5, 5 \n"
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".set reg_x6, 6 \n"
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".set reg_x7, 7 \n"
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".set reg_x8, 8 \n"
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".set reg_x9, 9 \n"
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".set reg_x10, 10 \n"
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".set reg_x11, 11 \n"
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".set reg_x12, 12 \n"
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".set reg_x13, 13 \n"
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".set reg_x14, 14 \n"
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".set reg_x15, 15 \n"
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#ifndef __riscv_32e
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".set reg_x16, 16 \n"
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".set reg_x17, 17 \n"
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".set reg_x18, 18 \n"
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".set reg_x19, 19 \n"
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".set reg_x20, 20 \n"
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".set reg_x21, 21 \n"
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".set reg_x22, 22 \n"
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".set reg_x23, 23 \n"
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".set reg_x24, 24 \n"
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".set reg_x25, 25 \n"
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".set reg_x26, 26 \n"
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".set reg_x27, 27 \n"
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".set reg_x28, 28 \n"
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".set reg_x29, 29 \n"
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".set reg_x30, 30 \n"
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".set reg_x31, 31 \n"
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#endif
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".set reg_zero, 0 \n"
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".set reg_ra, 1 \n"
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".set reg_sp, 2 \n"
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".set reg_gp, 3 \n"
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".set reg_tp, 4 \n"
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".set reg_t0, 5 \n"
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".set reg_t1, 6 \n"
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".set reg_t2, 7 \n"
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".set reg_s0, 8 \n"
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".set reg_s1, 9 \n"
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".set reg_a0, 10 \n"
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".set reg_a1, 11 \n"
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".set reg_a2, 12 \n"
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".set reg_a3, 13 \n"
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".set reg_a4, 14 \n"
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".set reg_a5, 15 \n"
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#ifndef __riscv_32e
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".set reg_a6, 16 \n"
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".set reg_a7, 17 \n"
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".set reg_s2, 18 \n"
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".set reg_s3, 19 \n"
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".set reg_s4, 20 \n"
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".set reg_s5, 21 \n"
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".set reg_s6, 22 \n"
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".set reg_s7, 23 \n"
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".set reg_s8, 24 \n"
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".set reg_s9, 25 \n"
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".set reg_s10, 26 \n"
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".set reg_s11, 27 \n"
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".set reg_t3, 28 \n"
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".set reg_t4, 29 \n"
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".set reg_t5, 30 \n"
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".set reg_t6, 31 \n"
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#endif
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);
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/**********************************************************************/
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#define CUSTOM_INSTR_R2_TYPE(funct7, funct5, rs1, funct3, opcode) \
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({ \
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uint32_t __return; \
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asm volatile( \
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".word ( \
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(((" #funct7 ") & 0x7f) << 25) | \
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(((" #funct5 ") & 0x1f) << 20) | \
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((( reg_%1 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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((( reg_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1) \
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); \
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__return; \
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})
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/**********************************************************************/
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#define CUSTOM_INSTR_R3_TYPE(funct7, rs2, rs1, funct3, opcode) \
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({ \
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uint32_t __return; \
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asm volatile ( \
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".word ( \
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(((" #funct7 ") & 0x7f) << 25) | \
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((( reg_%2 ) & 0x1f) << 20) | \
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((( reg_%1 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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((( reg_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1), \
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"r" (rs2) \
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); \
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__return; \
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})
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/**********************************************************************/
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#define CUSTOM_INSTR_R4_TYPE(rs3, rs2, rs1, funct3, opcode) \
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({ \
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uint32_t __return; \
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asm volatile ( \
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".word ( \
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((( reg_%3 ) & 0x1f) << 27) | \
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((( reg_%2 ) & 0x1f) << 20) | \
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((( reg_%1 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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((( reg_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1), \
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"r" (rs2), \
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"r" (rs3) \
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); \
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__return; \
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})
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/**********************************************************************/
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#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) \
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({ \
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uint32_t __return; \
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asm volatile ( \
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".word ( \
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(((" #imm12 ") & 0xfff) << 20) | \
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((( reg_%1 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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((( reg_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1) \
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); \
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__return; \
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})
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/**********************************************************************/
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#define CUSTOM_INSTR_S_TYPE(imm12, rs2, rs1, funct3, opcode) \
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({ \
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asm volatile ( \
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".word ( \
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((((" #imm12 ") >> 5) & 0x7f) << 25) | \
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((( reg_%1 ) & 0x1f) << 20) | \
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((( reg_%0 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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(((" #imm12 ") & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: \
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: "r" (rs1), \
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"r" (rs2) \
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); \
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})
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#endif
// NEORV32_INTRINSICS_H
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