neorv32_trng.h

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// ================================================================================ //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
// Copyright (c) NEORV32 contributors.                                              //
// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  //
// Licensed under the BSD-3-Clause license, see LICENSE for details.                //
// SPDX-License-Identifier: BSD-3-Clause                                            //
// ================================================================================ //
 
#ifndef neorv32_trng_h
#define neorv32_trng_h
 
#include <stdint.h>
 
 
/**********************************************************************/
typedef volatile struct __attribute__((packed,aligned(4))) {
  uint32_t       CTRL; 
  const uint32_t DATA; 
} neorv32_trng_t;
 
#define NEORV32_TRNG ((neorv32_trng_t*) (NEORV32_TRNG_BASE))
 
enum NEORV32_TRNG_CTRL_enum {
  TRNG_CTRL_EN       = 0, 
  TRNG_CTRL_FIFO_CLR = 1, 
  TRNG_CTRL_FIFO_LSB = 2, 
  TRNG_CTRL_FIFO_MSB = 5, 
  TRNG_CTRL_SIM_MODE = 6, 
  TRNG_CTRL_AVAIL    = 7  
};
 
enum NEORV32_TRNG_DATA_enum {
  TRNG_DATA_LSB = 0, 
  TRNG_DATA_MSB = 7  
};
/**********************************************************************/
int  neorv32_trng_available(void);
void neorv32_trng_enable(void);
void neorv32_trng_disable(void);
void neorv32_trng_fifo_clear(void);
int  neorv32_trng_get_fifo_depth(void);
int  neorv32_trng_get(uint8_t *data);
int  neorv32_trng_check_sim_mode(void);
#endif // neorv32_trng_h