neorv32_trng.h

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// ================================================================================ //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
// Copyright (c) NEORV32 contributors.                                              //
// Copyright (c) 2020 - 2026 Stephan Nolting. All rights reserved.                  //
// Licensed under the BSD-3-Clause license, see LICENSE for details.                //
// SPDX-License-Identifier: BSD-3-Clause                                            //
// ================================================================================ //

 
#ifndef NEORV32_TRNG_H
#define NEORV32_TRNG_H
 
#include <neorv32.h>
#include <stdint.h>
 
/**********************************************************************/
typedef volatile struct __attribute__((packed,aligned(4))) {
  uint32_t       CTRL; 
  const uint32_t DATA; 
} neorv32_trng_t;

#define NEORV32_TRNG ((neorv32_trng_t*) (NEORV32_TRNG_BASE))

enum NEORV32_TRNG_CTRL_enum {
  TRNG_CTRL_EN       =  0, 
  TRNG_CTRL_FIFO_CLR =  1, 
  TRNG_CTRL_SIM_MODE =  2, 
  TRNG_CTRL_AVAIL    =  3, 
  TRNG_CTRL_FIFO_LSB =  4, 
  TRNG_CTRL_FIFO_MSB =  7, 
  TRNG_CTRL_NBIT_LSB =  8, 
  TRNG_CTRL_NBIT_MSB = 11, 
  TRNG_CTRL_NRO_LSB  = 12, 
  TRNG_CTRL_NRO_MSB  = 19, 
  TRNG_CTRL_NINV_LSB = 20, 
  TRNG_CTRL_NINV_MSB = 31  
};

enum NEORV32_TRNG_DATA_enum {
  TRNG_DATA_LSB = 0, 
  TRNG_DATA_MSB = 7  
};

 
 
/**********************************************************************/
int     neorv32_trng_available(void);
void    neorv32_trng_enable(void);
void    neorv32_trng_disable(void);
void    neorv32_trng_fifo_clear(void);
int     neorv32_trng_get_fifo_depth(void);
int     neorv32_trng_get_num_raw_bits(void);
int     neorv32_trng_get_num_ros(void);
int     neorv32_trng_get_num_inv(void);
int     neorv32_trng_data_avail(void);
uint8_t neorv32_trng_data_get(void);
int     neorv32_trng_check_sim_mode(void);
 
 
#endif // NEORV32_TRNG_H