neorv32.h File Reference

Main NEORV32 core library include file. More...

#include <stdint.h>
#include <inttypes.h>
#include <limits.h>
#include <unistd.h>
#include <stdlib.h>
#include "neorv32_intrinsics.h"
#include "neorv32_cpu.h"
#include "neorv32_cpu_csr.h"
#include "neorv32_cpu_cfu.h"
#include "neorv32_rte.h"
#include "neorv32_buskeeper.h"
#include "neorv32_cfs.h"
#include "neorv32_dm.h"
#include "neorv32_gpio.h"
#include "neorv32_gptmr.h"
#include "neorv32_mtime.h"
#include "neorv32_neoled.h"
#include "neorv32_onewire.h"
#include "neorv32_pwm.h"
#include "neorv32_sdi.h"
#include "neorv32_spi.h"
#include "neorv32_sysinfo.h"
#include "neorv32_trng.h"
#include "neorv32_twi.h"
#include "neorv32_uart.h"
#include "neorv32_wdt.h"
#include "neorv32_xip.h"
#include "neorv32_xirq.h"
#include "legacy.h"

Go to the source code of this file.

Macros
#define	NEORV32_ARCHID   19
Watchdog Timer (WDT)
#define	WDT_FIRQ_ENABLE   CSR_MIE_FIRQ0E
#define	WDT_FIRQ_PENDING   CSR_MIP_FIRQ0P
#define	WDT_RTE_ID   RTE_TRAP_FIRQ_0
#define	WDT_TRAP_CODE   TRAP_CODE_FIRQ_0
Custom Functions Subsystem (CFS)
#define	CFS_FIRQ_ENABLE   CSR_MIE_FIRQ1E
#define	CFS_FIRQ_PENDING   CSR_MIP_FIRQ1P
#define	CFS_RTE_ID   RTE_TRAP_FIRQ_1
#define	CFS_TRAP_CODE   TRAP_CODE_FIRQ_1
Primary Universal Asynchronous Receiver/Transmitter (UART0)
#define	UART0_RX_FIRQ_ENABLE   CSR_MIE_FIRQ2E
#define	UART0_RX_FIRQ_PENDING   CSR_MIP_FIRQ2P
#define	UART0_RX_RTE_ID   RTE_TRAP_FIRQ_2
#define	UART0_RX_TRAP_CODE   TRAP_CODE_FIRQ_2
#define	UART0_TX_FIRQ_ENABLE   CSR_MIE_FIRQ3E
#define	UART0_TX_FIRQ_PENDING   CSR_MIP_FIRQ3P
#define	UART0_TX_RTE_ID   RTE_TRAP_FIRQ_3
#define	UART0_TX_TRAP_CODE   TRAP_CODE_FIRQ_3
Secondary Universal Asynchronous Receiver/Transmitter (UART1)
#define	UART1_RX_FIRQ_ENABLE   CSR_MIE_FIRQ4E
#define	UART1_RX_FIRQ_PENDING   CSR_MIP_FIRQ4P
#define	UART1_RX_RTE_ID   RTE_TRAP_FIRQ_4
#define	UART1_RX_TRAP_CODE   TRAP_CODE_FIRQ_4
#define	UART1_TX_FIRQ_ENABLE   CSR_MIE_FIRQ5E
#define	UART1_TX_FIRQ_PENDING   CSR_MIP_FIRQ5P
#define	UART1_TX_RTE_ID   RTE_TRAP_FIRQ_5
#define	UART1_TX_TRAP_CODE   TRAP_CODE_FIRQ_5
Serial Peripheral Interface (SPI)
#define	SPI_FIRQ_ENABLE   CSR_MIE_FIRQ6E
#define	SPI_FIRQ_PENDING   CSR_MIP_FIRQ6P
#define	SPI_RTE_ID   RTE_TRAP_FIRQ_6
#define	SPI_TRAP_CODE   TRAP_CODE_FIRQ_6
Two-Wire Interface (TWI)
#define	TWI_FIRQ_ENABLE   CSR_MIE_FIRQ7E
#define	TWI_FIRQ_PENDING   CSR_MIP_FIRQ7P
#define	TWI_RTE_ID   RTE_TRAP_FIRQ_7
#define	TWI_TRAP_CODE   TRAP_CODE_FIRQ_7
External Interrupt Controller (XIRQ)
#define	XIRQ_FIRQ_ENABLE   CSR_MIE_FIRQ8E
#define	XIRQ_FIRQ_PENDING   CSR_MIP_FIRQ8P
#define	XIRQ_RTE_ID   RTE_TRAP_FIRQ_8
#define	XIRQ_TRAP_CODE   TRAP_CODE_FIRQ_8
Smart LED Controller (NEOLED)
#define	NEOLED_FIRQ_ENABLE   CSR_MIE_FIRQ9E
#define	NEOLED_FIRQ_PENDING   CSR_MIP_FIRQ9P
#define	NEOLED_RTE_ID   RTE_TRAP_FIRQ_9
#define	NEOLED_TRAP_CODE   TRAP_CODE_FIRQ_9
Serial Data Interface (SDI)
#define	SDI_FIRQ_ENABLE   CSR_MIE_FIRQ11E
#define	SDI_FIRQ_PENDING   CSR_MIP_FIRQ11P
#define	SDI_RTE_ID   RTE_TRAP_FIRQ_11
#define	SDI_TRAP_CODE   TRAP_CODE_FIRQ_11
General Purpose Timer (GPTMR)
#define	GPTMR_FIRQ_ENABLE   CSR_MIE_FIRQ12E
#define	GPTMR_FIRQ_PENDING   CSR_MIP_FIRQ12P
#define	GPTMR_RTE_ID   RTE_TRAP_FIRQ_12
#define	GPTMR_TRAP_CODE   TRAP_CODE_FIRQ_12
1-Wire Interface Controller (ONEWIRE)
#define	ONEWIRE_FIRQ_ENABLE   CSR_MIE_FIRQ13E
#define	ONEWIRE_FIRQ_PENDING   CSR_MIP_FIRQ13P
#define	ONEWIRE_RTE_ID   RTE_TRAP_FIRQ_13
#define	ONEWIRE_TRAP_CODE   TRAP_CODE_FIRQ_13
Address space sections
#define	BOOTLOADER_BASE_ADDRESS   (0xFFFF0000U)
#define	OCD_BASE_ADDRESS   (0XFFFFF800U)
#define	IO_BASE_ADDRESS   (0xFFFFFE00U)
Peripheral/IO Devices - IO Address Space - base addresses
#define	NEORV32_SYSINFO_BASE   (0xFFFFFFE0U)
#define	NEORV32_NEOLED_BASE   (0xFFFFFFD8U)
#define	NEORV32_UART1_BASE   (0xFFFFFFD0U)
#define	NEORV32_GPIO_BASE   (0xFFFFFFC0U)
#define	NEORV32_WDT_BASE   (0xFFFFFFBCU)
#define	NEORV32_TRNG_BASE   (0xFFFFFFB8U)
#define	NEORV32_TWI_BASE   (0xFFFFFFB0U)
#define	NEORV32_SPI_BASE   (0xFFFFFFA8U)
#define	NEORV32_UART0_BASE   (0xFFFFFFA0U)
#define	NEORV32_MTIME_BASE   (0xFFFFFF90U)
#define	NEORV32_XIRQ_BASE   (0xFFFFFF80U)
#define	NEORV32_BUSKEEPER_BASE   (0xFFFFFF78U)
#define	NEORV32_ONEWIRE_BASE   (0xFFFFFF70U)
#define	NEORV32_GPTMR_BASE   (0xFFFFFF60U)
#define	NEORV32_PWM_BASE   (0xFFFFFF50U)
#define	NEORV32_XIP_BASE   (0xFFFFFF40U)
#define	NEORV32_SDI_BASE   (0xFFFFFF00U)
#define	NEORV32_CFS_BASE   (0xFFFFFE00U)
#define	NEORV32_DM_BASE   (0xFFFFF800U)

Enumerations
enum	NEORV32_CLOCK_PRSC_enum {   CLK_PRSC_2 = 0 , CLK_PRSC_4 = 1 , CLK_PRSC_8 = 2 , CLK_PRSC_64 = 3 ,   CLK_PRSC_128 = 4 , CLK_PRSC_1024 = 5 , CLK_PRSC_2048 = 6 , CLK_PRSC_4096 = 7 }

Detailed Description

Main NEORV32 core library include file.

Author

Stephan Nolting

Macro Definition Documentation

BOOTLOADER_BASE_ADDRESS

#define BOOTLOADER_BASE_ADDRESS   (0xFFFF0000U)

bootloader memory base address

CFS_FIRQ_ENABLE

#define CFS_FIRQ_ENABLE   CSR_MIE_FIRQ1E

MIE CSR bit (NEORV32_CSR_MIE_enum)

CFS_FIRQ_PENDING

#define CFS_FIRQ_PENDING   CSR_MIP_FIRQ1P

MIP CSR bit (NEORV32_CSR_MIP_enum)

CFS_RTE_ID

#define CFS_RTE_ID   RTE_TRAP_FIRQ_1

RTE entry code (NEORV32_RTE_TRAP_enum)

CFS_TRAP_CODE

#define CFS_TRAP_CODE   TRAP_CODE_FIRQ_1

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

GPTMR_FIRQ_ENABLE

#define GPTMR_FIRQ_ENABLE   CSR_MIE_FIRQ12E

MIE CSR bit (NEORV32_CSR_MIE_enum)

GPTMR_FIRQ_PENDING

#define GPTMR_FIRQ_PENDING   CSR_MIP_FIRQ12P

MIP CSR bit (NEORV32_CSR_MIP_enum)

GPTMR_RTE_ID

#define GPTMR_RTE_ID   RTE_TRAP_FIRQ_12

RTE entry code (NEORV32_RTE_TRAP_enum)

GPTMR_TRAP_CODE

#define GPTMR_TRAP_CODE   TRAP_CODE_FIRQ_12

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

IO_BASE_ADDRESS

#define IO_BASE_ADDRESS   (0xFFFFFE00U)

peripheral/IO devices memory base address

NEOLED_FIRQ_ENABLE

#define NEOLED_FIRQ_ENABLE   CSR_MIE_FIRQ9E

MIE CSR bit (NEORV32_CSR_MIE_enum)

NEOLED_FIRQ_PENDING

#define NEOLED_FIRQ_PENDING   CSR_MIP_FIRQ9P

MIP CSR bit (NEORV32_CSR_MIP_enum)

NEOLED_RTE_ID

#define NEOLED_RTE_ID   RTE_TRAP_FIRQ_9

RTE entry code (NEORV32_RTE_TRAP_enum)

NEOLED_TRAP_CODE

#define NEOLED_TRAP_CODE   TRAP_CODE_FIRQ_9

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

NEORV32_ARCHID

#define NEORV32_ARCHID   19

Official NEORV32 RISC-V open-source architecture ID https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md

NEORV32_BUSKEEPER_BASE

#define NEORV32_BUSKEEPER_BASE   (0xFFFFFF78U)

Bus Monitor (BUSKEEPER)

NEORV32_CFS_BASE

#define NEORV32_CFS_BASE   (0xFFFFFE00U)

Custom Functions Subsystem (CFS)

NEORV32_DM_BASE

#define NEORV32_DM_BASE   (0xFFFFF800U)

On-Chip Debugger

NEORV32_GPIO_BASE

#define NEORV32_GPIO_BASE   (0xFFFFFFC0U)

General Purpose Input/Output Port Unit (GPIO)

NEORV32_GPTMR_BASE

#define NEORV32_GPTMR_BASE   (0xFFFFFF60U)

General Purpose Timer (GPTMR)

NEORV32_MTIME_BASE

#define NEORV32_MTIME_BASE   (0xFFFFFF90U)

Machine System Timer (MTIME)

NEORV32_NEOLED_BASE

#define NEORV32_NEOLED_BASE   (0xFFFFFFD8U)

Smart LED Hardware Interface (NEOLED)

NEORV32_ONEWIRE_BASE

#define NEORV32_ONEWIRE_BASE   (0xFFFFFF70U)

1-Wire Interface Controller (ONEWIRE)

NEORV32_PWM_BASE

#define NEORV32_PWM_BASE   (0xFFFFFF50U)

Pulse Width Modulation Controller (PWM)

NEORV32_SDI_BASE

#define NEORV32_SDI_BASE   (0xFFFFFF00U)

Serial Data Interface (SDI)

NEORV32_SPI_BASE

#define NEORV32_SPI_BASE   (0xFFFFFFA8U)

Serial Peripheral Interface Controller (SPI)

NEORV32_SYSINFO_BASE

#define NEORV32_SYSINFO_BASE   (0xFFFFFFE0U)

System Configuration Information Memory (SYSINFO)

NEORV32_TRNG_BASE

#define NEORV32_TRNG_BASE   (0xFFFFFFB8U)

True Random Number Generator (TRNG)

NEORV32_TWI_BASE

#define NEORV32_TWI_BASE   (0xFFFFFFB0U)

Two-Wire Interface Controller (TWI)

NEORV32_UART0_BASE

#define NEORV32_UART0_BASE   (0xFFFFFFA0U)

Primary Universal Asynchronous Receiver and Transmitter (UART0)

NEORV32_UART1_BASE

#define NEORV32_UART1_BASE   (0xFFFFFFD0U)

Secondary Universal Asynchronous Receiver and Transmitter (UART1)

NEORV32_WDT_BASE

#define NEORV32_WDT_BASE   (0xFFFFFFBCU)

Watchdog Timer (WDT)

NEORV32_XIP_BASE

#define NEORV32_XIP_BASE   (0xFFFFFF40U)

Execute In Place Module (XIP)

NEORV32_XIRQ_BASE

#define NEORV32_XIRQ_BASE   (0xFFFFFF80U)

External Interrupt Controller (XIRQ)

OCD_BASE_ADDRESS

#define OCD_BASE_ADDRESS   (0XFFFFF800U)

on-chip debugger complex base address

ONEWIRE_FIRQ_ENABLE

#define ONEWIRE_FIRQ_ENABLE   CSR_MIE_FIRQ13E

MIE CSR bit (NEORV32_CSR_MIE_enum)

ONEWIRE_FIRQ_PENDING

#define ONEWIRE_FIRQ_PENDING   CSR_MIP_FIRQ13P

MIP CSR bit (NEORV32_CSR_MIP_enum)

ONEWIRE_RTE_ID

#define ONEWIRE_RTE_ID   RTE_TRAP_FIRQ_13

RTE entry code (NEORV32_RTE_TRAP_enum)

ONEWIRE_TRAP_CODE

#define ONEWIRE_TRAP_CODE   TRAP_CODE_FIRQ_13

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

SDI_FIRQ_ENABLE

#define SDI_FIRQ_ENABLE   CSR_MIE_FIRQ11E

MIE CSR bit (NEORV32_CSR_MIE_enum)

SDI_FIRQ_PENDING

#define SDI_FIRQ_PENDING   CSR_MIP_FIRQ11P

MIP CSR bit (NEORV32_CSR_MIP_enum)

SDI_RTE_ID

#define SDI_RTE_ID   RTE_TRAP_FIRQ_11

RTE entry code (NEORV32_RTE_TRAP_enum)

SDI_TRAP_CODE

#define SDI_TRAP_CODE   TRAP_CODE_FIRQ_11

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

SPI_FIRQ_ENABLE

#define SPI_FIRQ_ENABLE   CSR_MIE_FIRQ6E

MIE CSR bit (NEORV32_CSR_MIE_enum)

SPI_FIRQ_PENDING

#define SPI_FIRQ_PENDING   CSR_MIP_FIRQ6P

MIP CSR bit (NEORV32_CSR_MIP_enum)

SPI_RTE_ID

#define SPI_RTE_ID   RTE_TRAP_FIRQ_6

RTE entry code (NEORV32_RTE_TRAP_enum)

SPI_TRAP_CODE

#define SPI_TRAP_CODE   TRAP_CODE_FIRQ_6

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

TWI_FIRQ_ENABLE

#define TWI_FIRQ_ENABLE   CSR_MIE_FIRQ7E

MIE CSR bit (NEORV32_CSR_MIE_enum)

TWI_FIRQ_PENDING

#define TWI_FIRQ_PENDING   CSR_MIP_FIRQ7P

MIP CSR bit (NEORV32_CSR_MIP_enum)

TWI_RTE_ID

#define TWI_RTE_ID   RTE_TRAP_FIRQ_7

RTE entry code (NEORV32_RTE_TRAP_enum)

TWI_TRAP_CODE

#define TWI_TRAP_CODE   TRAP_CODE_FIRQ_7

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

UART0_RX_FIRQ_ENABLE

#define UART0_RX_FIRQ_ENABLE   CSR_MIE_FIRQ2E

MIE CSR bit (NEORV32_CSR_MIE_enum)

UART0_RX_FIRQ_PENDING

#define UART0_RX_FIRQ_PENDING   CSR_MIP_FIRQ2P

MIP CSR bit (NEORV32_CSR_MIP_enum)

UART0_RX_RTE_ID

#define UART0_RX_RTE_ID   RTE_TRAP_FIRQ_2

RTE entry code (NEORV32_RTE_TRAP_enum)

UART0_RX_TRAP_CODE

#define UART0_RX_TRAP_CODE   TRAP_CODE_FIRQ_2

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

UART0_TX_FIRQ_ENABLE

#define UART0_TX_FIRQ_ENABLE   CSR_MIE_FIRQ3E

MIE CSR bit (NEORV32_CSR_MIE_enum)

UART0_TX_FIRQ_PENDING

#define UART0_TX_FIRQ_PENDING   CSR_MIP_FIRQ3P

MIP CSR bit (NEORV32_CSR_MIP_enum)

UART0_TX_RTE_ID

#define UART0_TX_RTE_ID   RTE_TRAP_FIRQ_3

RTE entry code (NEORV32_RTE_TRAP_enum)

UART0_TX_TRAP_CODE

#define UART0_TX_TRAP_CODE   TRAP_CODE_FIRQ_3

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

UART1_RX_FIRQ_ENABLE

#define UART1_RX_FIRQ_ENABLE   CSR_MIE_FIRQ4E

MIE CSR bit (NEORV32_CSR_MIE_enum)

UART1_RX_FIRQ_PENDING

#define UART1_RX_FIRQ_PENDING   CSR_MIP_FIRQ4P

MIP CSR bit (NEORV32_CSR_MIP_enum)

UART1_RX_RTE_ID

#define UART1_RX_RTE_ID   RTE_TRAP_FIRQ_4

RTE entry code (NEORV32_RTE_TRAP_enum)

UART1_RX_TRAP_CODE

#define UART1_RX_TRAP_CODE   TRAP_CODE_FIRQ_4

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

UART1_TX_FIRQ_ENABLE

#define UART1_TX_FIRQ_ENABLE   CSR_MIE_FIRQ5E

MIE CSR bit (NEORV32_CSR_MIE_enum)

UART1_TX_FIRQ_PENDING

#define UART1_TX_FIRQ_PENDING   CSR_MIP_FIRQ5P

MIP CSR bit (NEORV32_CSR_MIP_enum)

UART1_TX_RTE_ID

#define UART1_TX_RTE_ID   RTE_TRAP_FIRQ_5

RTE entry code (NEORV32_RTE_TRAP_enum)

UART1_TX_TRAP_CODE

#define UART1_TX_TRAP_CODE   TRAP_CODE_FIRQ_5

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

WDT_FIRQ_ENABLE

#define WDT_FIRQ_ENABLE   CSR_MIE_FIRQ0E

MIE CSR bit (NEORV32_CSR_MIE_enum)

WDT_FIRQ_PENDING

#define WDT_FIRQ_PENDING   CSR_MIP_FIRQ0P

MIP CSR bit (NEORV32_CSR_MIP_enum)

WDT_RTE_ID

#define WDT_RTE_ID   RTE_TRAP_FIRQ_0

RTE entry code (NEORV32_RTE_TRAP_enum)

WDT_TRAP_CODE

#define WDT_TRAP_CODE   TRAP_CODE_FIRQ_0

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

XIRQ_FIRQ_ENABLE

#define XIRQ_FIRQ_ENABLE   CSR_MIE_FIRQ8E

MIE CSR bit (NEORV32_CSR_MIE_enum)

XIRQ_FIRQ_PENDING

#define XIRQ_FIRQ_PENDING   CSR_MIP_FIRQ8P

MIP CSR bit (NEORV32_CSR_MIP_enum)

XIRQ_RTE_ID

#define XIRQ_RTE_ID   RTE_TRAP_FIRQ_8

RTE entry code (NEORV32_RTE_TRAP_enum)

XIRQ_TRAP_CODE

#define XIRQ_TRAP_CODE   TRAP_CODE_FIRQ_8

MCAUSE CSR trap code (NEORV32_EXCEPTION_CODES_enum)

Enumeration Type Documentation

NEORV32_CLOCK_PRSC_enum

enum NEORV32_CLOCK_PRSC_enum

Processor clock prescaler select

Enumerator
CLK_PRSC_2	CPU_CLK (from clk_i top signal) / 2
CLK_PRSC_4	CPU_CLK (from clk_i top signal) / 4
CLK_PRSC_8	CPU_CLK (from clk_i top signal) / 8
CLK_PRSC_64	CPU_CLK (from clk_i top signal) / 64
CLK_PRSC_128	CPU_CLK (from clk_i top signal) / 128
CLK_PRSC_1024	CPU_CLK (from clk_i top signal) / 1024
CLK_PRSC_2048	CPU_CLK (from clk_i top signal) / 2048
CLK_PRSC_4096	CPU_CLK (from clk_i top signal) / 4096