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NEORV32 - Software Framework Documentation
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Execute in place module (XIP) HW driver source file. More...
Functions | |
int | neorv32_xip_available (void) |
void | neorv32_xip_setup (int prsc, int cdiv, int cpol, int cpha, uint8_t rd_cmd) |
int | neorv32_xip_start (int abytes) |
void | neorv32_xip_highspeed_enable (void) |
void | neorv32_xip_highspeed_disable (void) |
uint32_t | neorv32_xip_get_clock_speed (void) |
void | neorv32_xip_burst_mode_enable (void) |
void | neorv32_xip_burst_mode_disable (void) |
void | neorv32_xip_spi_trans (int nbytes, uint64_t *rtx_data) |
Execute in place module (XIP) HW driver source file.
int neorv32_xip_available | ( | void | ) |
Check if XIP module was synthesized.
void neorv32_xip_burst_mode_disable | ( | void | ) |
Disable XIP burst mode.
void neorv32_xip_burst_mode_enable | ( | void | ) |
Enable XIP burst mode (incremental reads).
uint32_t neorv32_xip_get_clock_speed | ( | void | ) |
Get configured clock speed in Hz.
void neorv32_xip_highspeed_disable | ( | void | ) |
Disable high-speed SPI mode.
void neorv32_xip_highspeed_enable | ( | void | ) |
Enable high-speed SPI mode (running at half of the processor clock).
void neorv32_xip_setup | ( | int | prsc, |
int | cdiv, | ||
int | cpol, | ||
int | cpha, | ||
uint8_t | rd_cmd | ||
) |
Configure XIP module: configure SPI/flash properties.
[in] | prsc | SPI clock prescaler select (0..7). @prama[in] cdiv Clock divider (0..15). |
[in] | cpol | SPI clock polarity (0/1). |
[in] | cpha | SPI clock phase(0/1). |
[in] | rd_cmd | SPI flash read byte command. |
void neorv32_xip_spi_trans | ( | int | nbytes, |
uint64_t * | rtx_data | ||
) |
Direct SPI access to the XIP flash.
[in] | nbytes | Number of bytes to transfer (1..8). |
[in,out] | rtx_data | Pointer to 64-bit TX/RX data (MSB-aligned for sending, LSB-aligned for receiving (only 32-bit)). |
int neorv32_xip_start | ( | int | abytes | ) |
Enable XIP mode (to allow CPU to transparently fetch data & instructions).
[in] | abytes | Number of address bytes used to access the SPI flash (1,2,3,4). |