NEORV32 - Software Framework Documentation
neorv32.h
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1// #################################################################################################
2// # << NEORV32: neorv32.h - Main Core Library File >> #
3// # ********************************************************************************************* #
4// # BSD 3-Clause License #
5// # #
6// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
7// # #
8// # Redistribution and use in source and binary forms, with or without modification, are #
9// # permitted provided that the following conditions are met: #
10// # #
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12// # conditions and the following disclaimer. #
13// # #
14// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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31// # ********************************************************************************************* #
32// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
33// #################################################################################################
34
35
36/**********************************************************************/
43#ifndef neorv32_h
44#define neorv32_h
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50
51// Standard libraries
52#include <stdint.h>
53#include <inttypes.h>
54#include <limits.h>
55#include <unistd.h>
56#include <stdlib.h>
57
58
59/**********************************************************************/
63 /* hardware-only CSR, NEORV32-specific, not accessible by software */
64//CSR_ZERO = 0x000, /**< 0x000 - zero (-/-): Always zero */
65
66 /* floating-point unit control and status */
67 CSR_FFLAGS = 0x001,
68 CSR_FRM = 0x002,
69 CSR_FCSR = 0x003,
71 /* machine control and status */
72 CSR_MSTATUS = 0x300,
73 CSR_MISA = 0x301,
74 CSR_MIE = 0x304,
75 CSR_MTVEC = 0x305,
78 CSR_MENVCFG = 0x30a,
80 CSR_MSTATUSH = 0x310,
82 CSR_MENVCFGH = 0x31a,
86 /* hardware performance monitors - event configuration */
117 /* machine trap control */
118 CSR_MSCRATCH = 0x340,
119 CSR_MEPC = 0x341,
120 CSR_MCAUSE = 0x342,
121 CSR_MTVAL = 0x343,
122 CSR_MIP = 0x344,
124 /* physical memory protection */
125 CSR_PMPCFG0 = 0x3a0,
126 CSR_PMPCFG1 = 0x3a1,
127 CSR_PMPCFG2 = 0x3a2,
128 CSR_PMPCFG3 = 0x3a3,
130 CSR_PMPADDR0 = 0x3b0,
131 CSR_PMPADDR1 = 0x3b1,
132 CSR_PMPADDR2 = 0x3b2,
133 CSR_PMPADDR3 = 0x3b3,
134 CSR_PMPADDR4 = 0x3b4,
135 CSR_PMPADDR5 = 0x3b5,
136 CSR_PMPADDR6 = 0x3b6,
137 CSR_PMPADDR7 = 0x3b7,
138 CSR_PMPADDR8 = 0x3b8,
139 CSR_PMPADDR9 = 0x3b9,
147 /* on-chip debugger - hardware trigger module */
148 CSR_TSELECT = 0x7a0,
149 CSR_TDATA1 = 0x7a1,
150 CSR_TDATA2 = 0x7a2,
151 CSR_TDATA3 = 0x7a3,
152 CSR_TINFO = 0x7a4,
153 CSR_TCONTROL = 0x7a5,
154 CSR_MCONTEXT = 0x7a8,
155 CSR_SCONTEXT = 0x7aa,
157 /* not accessible by m-mode software */
158//CSR_DCSR = 0x7b0, /**< 0x7b0 - dcsr (-/-): Debug status and control register */
159//CSR_DPC = 0x7b1, /**< 0x7b1 - dpc (-/-): Debug program counter */
160//CSR_DSCRATCH = 0x7b2, /**< 0x7b2 - dscratch (-/-): Debug scratch register */
161
162 /* counter and timers - low word */
163 CSR_MCYCLE = 0xb00,
164 CSR_MINSTRET = 0xb02,
196 CSR_MCYCLEH = 0xb80,
229 CSR_CYCLE = 0xc00,
230 CSR_TIME = 0xc01,
231 CSR_INSTRET = 0xc02,
233 /* not implemented */
234//CSR_HPMCOUNTER3 = 0xc03, /**< 0xc03 - hpmcounter3 (r/-): User hardware performance monitor 3 counter low word */
235//CSR_HPMCOUNTER4 = 0xc04, /**< 0xc04 - hpmcounter4 (r/-): User hardware performance monitor 4 counter low word */
236//CSR_HPMCOUNTER5 = 0xc05, /**< 0xc05 - hpmcounter5 (r/-): User hardware performance monitor 5 counter low word */
237//CSR_HPMCOUNTER6 = 0xc06, /**< 0xc06 - hpmcounter6 (r/-): User hardware performance monitor 6 counter low word */
238//CSR_HPMCOUNTER7 = 0xc07, /**< 0xc07 - hpmcounter7 (r/-): User hardware performance monitor 7 counter low word */
239//CSR_HPMCOUNTER8 = 0xc08, /**< 0xc08 - hpmcounter8 (r/-): User hardware performance monitor 8 counter low word */
240//CSR_HPMCOUNTER9 = 0xc09, /**< 0xc09 - hpmcounter9 (r/-): User hardware performance monitor 9 counter low word */
241//CSR_HPMCOUNTER10 = 0xc0a, /**< 0xc0a - hpmcounter10 (r/-): User hardware performance monitor 10 counter low word */
242//CSR_HPMCOUNTER11 = 0xc0b, /**< 0xc0b - hpmcounter11 (r/-): User hardware performance monitor 11 counter low word */
243//CSR_HPMCOUNTER12 = 0xc0c, /**< 0xc0c - hpmcounter12 (r/-): User hardware performance monitor 12 counter low word */
244//CSR_HPMCOUNTER13 = 0xc0d, /**< 0xc0d - hpmcounter13 (r/-): User hardware performance monitor 13 counter low word */
245//CSR_HPMCOUNTER14 = 0xc0e, /**< 0xc0e - hpmcounter14 (r/-): User hardware performance monitor 14 counter low word */
246//CSR_HPMCOUNTER15 = 0xc0f, /**< 0xc0f - hpmcounter15 (r/-): User hardware performance monitor 15 counter low word */
247//CSR_HPMCOUNTER16 = 0xc10, /**< 0xc10 - hpmcounter16 (r/-): User hardware performance monitor 16 counter low word */
248//CSR_HPMCOUNTER17 = 0xc11, /**< 0xc11 - hpmcounter17 (r/-): User hardware performance monitor 17 counter low word */
249//CSR_HPMCOUNTER18 = 0xc12, /**< 0xc12 - hpmcounter18 (r/-): User hardware performance monitor 18 counter low word */
250//CSR_HPMCOUNTER19 = 0xc13, /**< 0xc13 - hpmcounter19 (r/-): User hardware performance monitor 19 counter low word */
251//CSR_HPMCOUNTER20 = 0xc14, /**< 0xc14 - hpmcounter20 (r/-): User hardware performance monitor 20 counter low word */
252//CSR_HPMCOUNTER21 = 0xc15, /**< 0xc15 - hpmcounter21 (r/-): User hardware performance monitor 21 counter low word */
253//CSR_HPMCOUNTER22 = 0xc16, /**< 0xc16 - hpmcounter22 (r/-): User hardware performance monitor 22 counter low word */
254//CSR_HPMCOUNTER23 = 0xc17, /**< 0xc17 - hpmcounter23 (r/-): User hardware performance monitor 23 counter low word */
255//CSR_HPMCOUNTER24 = 0xc18, /**< 0xc18 - hpmcounter24 (r/-): User hardware performance monitor 24 counter low word */
256//CSR_HPMCOUNTER25 = 0xc19, /**< 0xc19 - hpmcounter25 (r/-): User hardware performance monitor 25 counter low word */
257//CSR_HPMCOUNTER26 = 0xc1a, /**< 0xc1a - hpmcounter26 (r/-): User hardware performance monitor 26 counter low word */
258//CSR_HPMCOUNTER27 = 0xc1b, /**< 0xc1b - hpmcounter27 (r/-): User hardware performance monitor 27 counter low word */
259//CSR_HPMCOUNTER28 = 0xc1c, /**< 0xc1c - hpmcounter28 (r/-): User hardware performance monitor 28 counter low word */
260//CSR_HPMCOUNTER29 = 0xc1d, /**< 0xc1d - hpmcounter29 (r/-): User hardware performance monitor 29 counter low word */
261//CSR_HPMCOUNTER30 = 0xc1e, /**< 0xc1e - hpmcounter30 (r/-): User hardware performance monitor 30 counter low word */
262//CSR_HPMCOUNTER31 = 0xc1f, /**< 0xc1f - hpmcounter31 (r/-): User hardware performance monitor 31 counter low word */
263
264
265 /* counter and timers - high word */
266 CSR_CYCLEH = 0xc80,
267 CSR_TIMEH = 0xc81,
268 CSR_INSTRETH = 0xc82,
270 /* not implemented */
271//CSR_HPMCOUNTER3H = 0xc83, /**< 0xc83 - hpmcounter3h (r/-): User hardware performance monitor 3 counter high word */
272//CSR_HPMCOUNTER4H = 0xc84, /**< 0xc84 - hpmcounter4h (r/-): User hardware performance monitor 4 counter high word */
273//CSR_HPMCOUNTER5H = 0xc85, /**< 0xc85 - hpmcounter5h (r/-): User hardware performance monitor 5 counter high word */
274//CSR_HPMCOUNTER6H = 0xc86, /**< 0xc86 - hpmcounter6h (r/-): User hardware performance monitor 6 counter high word */
275//CSR_HPMCOUNTER7H = 0xc87, /**< 0xc87 - hpmcounter7h (r/-): User hardware performance monitor 7 counter high word */
276//CSR_HPMCOUNTER8H = 0xc88, /**< 0xc88 - hpmcounter8h (r/-): User hardware performance monitor 8 counter high word */
277//CSR_HPMCOUNTER9H = 0xc89, /**< 0xc89 - hpmcounter9h (r/-): User hardware performance monitor 9 counter high word */
278//CSR_HPMCOUNTER10H = 0xc8a, /**< 0xc8a - hpmcounter10h (r/-): User hardware performance monitor 10 counter high word */
279//CSR_HPMCOUNTER11H = 0xc8b, /**< 0xc8b - hpmcounter11h (r/-): User hardware performance monitor 11 counter high word */
280//CSR_HPMCOUNTER12H = 0xc8c, /**< 0xc8c - hpmcounter12h (r/-): User hardware performance monitor 12 counter high word */
281//CSR_HPMCOUNTER13H = 0xc8d, /**< 0xc8d - hpmcounter13h (r/-): User hardware performance monitor 13 counter high word */
282//CSR_HPMCOUNTER14H = 0xc8e, /**< 0xc8e - hpmcounter14h (r/-): User hardware performance monitor 14 counter high word */
283//CSR_HPMCOUNTER15H = 0xc8f, /**< 0xc8f - hpmcounter15h (r/-): User hardware performance monitor 15 counter high word */
284//CSR_HPMCOUNTER16H = 0xc90, /**< 0xc90 - hpmcounter16h (r/-): User hardware performance monitor 16 counter high word */
285//CSR_HPMCOUNTER17H = 0xc91, /**< 0xc91 - hpmcounter17h (r/-): User hardware performance monitor 17 counter high word */
286//CSR_HPMCOUNTER18H = 0xc92, /**< 0xc92 - hpmcounter18h (r/-): User hardware performance monitor 18 counter high word */
287//CSR_HPMCOUNTER19H = 0xc93, /**< 0xc93 - hpmcounter19h (r/-): User hardware performance monitor 19 counter high word */
288//CSR_HPMCOUNTER20H = 0xc94, /**< 0xc94 - hpmcounter20h (r/-): User hardware performance monitor 20 counter high word */
289//CSR_HPMCOUNTER21H = 0xc95, /**< 0xc95 - hpmcounter21h (r/-): User hardware performance monitor 21 counter high word */
290//CSR_HPMCOUNTER22H = 0xc96, /**< 0xc96 - hpmcounter22h (r/-): User hardware performance monitor 22 counter high word */
291//CSR_HPMCOUNTER23H = 0xc97, /**< 0xc97 - hpmcounter23h (r/-): User hardware performance monitor 23 counter high word */
292//CSR_HPMCOUNTER24H = 0xc98, /**< 0xc98 - hpmcounter24h (r/-): User hardware performance monitor 24 counter high word */
293//CSR_HPMCOUNTER25H = 0xc99, /**< 0xc99 - hpmcounter25h (r/-): User hardware performance monitor 25 counter high word */
294//CSR_HPMCOUNTER26H = 0xc9a, /**< 0xc9a - hpmcounter26h (r/-): User hardware performance monitor 26 counter high word */
295//CSR_HPMCOUNTER27H = 0xc9b, /**< 0xc9b - hpmcounter27h (r/-): User hardware performance monitor 27 counter high word */
296//CSR_HPMCOUNTER28H = 0xc9c, /**< 0xc9c - hpmcounter28h (r/-): User hardware performance monitor 28 counter high word */
297//CSR_HPMCOUNTER29H = 0xc9d, /**< 0xc9d - hpmcounter29h (r/-): User hardware performance monitor 29 counter high word */
298//CSR_HPMCOUNTER30H = 0xc9e, /**< 0xc9e - hpmcounter30h (r/-): User hardware performance monitor 30 counter high word */
299//CSR_HPMCOUNTER31H = 0xc9f, /**< 0xc9f - hpmcounter31h (r/-): User hardware performance monitor 31 counter high word */
300
301 /* machine information registers */
303 CSR_MARCHID = 0xf12,
304 CSR_MIMPID = 0xf13,
305 CSR_MHARTID = 0xf14,
308 CSR_MXISA = 0xfc0
310
311
312/**********************************************************************/
320 CSR_MSTATUS_TW = 21
322
323
324/**********************************************************************/
332
333
334/**********************************************************************/
371
372
373/**********************************************************************/
396 CSR_MIE_FIRQ15E = 31
398
399
400/**********************************************************************/
408 /* NEORV32-specific extension */
424 CSR_MIP_FIRQ15P = 31
426
427
428/**********************************************************************/
443 CSR_MISA_MXL_HI = 31
445
446
447/**********************************************************************/
451 // ISA (sub-)extensions
464 // Misc
468 // Tuning options
472
473
474/**********************************************************************/
496
497
498/**********************************************************************/
507 PMPCFG_L = 7
509
510/**********************************************************************/
515 PMP_TOR = 1
517
518
519/**********************************************************************/
523 TRAP_CODE_I_MISALIGNED = 0x00000000UL,
524 TRAP_CODE_I_ACCESS = 0x00000001UL,
525 TRAP_CODE_I_ILLEGAL = 0x00000002UL,
526 TRAP_CODE_BREAKPOINT = 0x00000003UL,
527 TRAP_CODE_L_MISALIGNED = 0x00000004UL,
528 TRAP_CODE_L_ACCESS = 0x00000005UL,
529 TRAP_CODE_S_MISALIGNED = 0x00000006UL,
530 TRAP_CODE_S_ACCESS = 0x00000007UL,
531 TRAP_CODE_UENV_CALL = 0x00000008UL,
532 TRAP_CODE_MENV_CALL = 0x0000000bUL,
533 TRAP_CODE_MSI = 0x80000003UL,
534 TRAP_CODE_MTI = 0x80000007UL,
535 TRAP_CODE_MEI = 0x8000000bUL,
536 TRAP_CODE_FIRQ_0 = 0x80000010UL,
537 TRAP_CODE_FIRQ_1 = 0x80000011UL,
538 TRAP_CODE_FIRQ_2 = 0x80000012UL,
539 TRAP_CODE_FIRQ_3 = 0x80000013UL,
540 TRAP_CODE_FIRQ_4 = 0x80000014UL,
541 TRAP_CODE_FIRQ_5 = 0x80000015UL,
542 TRAP_CODE_FIRQ_6 = 0x80000016UL,
543 TRAP_CODE_FIRQ_7 = 0x80000017UL,
544 TRAP_CODE_FIRQ_8 = 0x80000018UL,
545 TRAP_CODE_FIRQ_9 = 0x80000019UL,
546 TRAP_CODE_FIRQ_10 = 0x8000001aUL,
547 TRAP_CODE_FIRQ_11 = 0x8000001bUL,
548 TRAP_CODE_FIRQ_12 = 0x8000001cUL,
549 TRAP_CODE_FIRQ_13 = 0x8000001dUL,
550 TRAP_CODE_FIRQ_14 = 0x8000001eUL,
551 TRAP_CODE_FIRQ_15 = 0x8000001fUL
553
554
555/**********************************************************************/
566 CLK_PRSC_4096 = 7
568
569
570/**********************************************************************/
574#define NEORV32_ARCHID 19
575
576
577/**********************************************************************/
584#define WDT_FIRQ_ENABLE CSR_MIE_FIRQ0E
585#define WDT_FIRQ_PENDING CSR_MIP_FIRQ0P
586#define WDT_RTE_ID RTE_TRAP_FIRQ_0
587#define WDT_TRAP_CODE TRAP_CODE_FIRQ_0
591#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E
592#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P
593#define CFS_RTE_ID RTE_TRAP_FIRQ_1
594#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1
598#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E
599#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P
600#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2
601#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2
602#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E
603#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P
604#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3
605#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_4
609#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E
610#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P
611#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4
612#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4
613#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E
614#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P
615#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5
616#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5
620#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E
621#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P
622#define SPI_RTE_ID RTE_TRAP_FIRQ_6
623#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6
627#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E
628#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P
629#define TWI_RTE_ID RTE_TRAP_FIRQ_7
630#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7
634#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E
635#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P
636#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8
637#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8
641#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E
642#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P
643#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9
644#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9
648#define SLINK_RX_FIRQ_ENABLE CSR_MIE_FIRQ10E
649#define SLINK_RX_FIRQ_PENDING CSR_MIP_FIRQ10P
650#define SLINK_RX_RTE_ID RTE_TRAP_FIRQ_10
651#define SLINK_RX_TRAP_CODE TRAP_CODE_FIRQ_10
652#define SLINK_TX_FIRQ_ENABLE CSR_MIE_FIRQ11E
653#define SLINK_TX_FIRQ_PENDING CSR_MIP_FIRQ11P
654#define SLINK_TX_RTE_ID RTE_TRAP_FIRQ_11
655#define SLINK_TX_TRAP_CODE TRAP_CODE_FIRQ_11
659#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E
660#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P
661#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12
662#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12
667/**********************************************************************/
672// -> configured via 'ispace_base_c' constant in neorv32_package.vhd and available to software via SYSINFO entry
674// -> configured via 'dspace_base_c' constant in neorv32_package.vhd and available to software via SYSINFO entry
676#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
678#define OCD_BASE_ADDRESS (0XFFFFF800UL)
680#define IO_BASE_ADDRESS (0xFFFFFE00UL)
684// ############################################################################################################################
685// On-Chip Debugger (should NOT be used by application software at all!)
686// ############################################################################################################################
689typedef struct __attribute__((packed,aligned(4))) {
690 const uint32_t CODE[32];
691 const uint32_t PBUF[4];
692 const uint32_t reserved1[28];
693 uint32_t DATA;
694 const uint32_t reserved2[31];
695 uint32_t SREG;
696 const uint32_t reserved3[31];
698
700#define NEORV32_DM_BASE (0XFFFFF800UL)
701
703#define NEORV32_DM (*((volatile neorv32_dm_t*) (NEORV32_DM_BASE)))
704
717// ############################################################################################################################
718// Peripheral/IO Devices - IO Address Space
719// ############################################################################################################################
720
721
722/**********************************************************************/
727#define IO_REG8 (volatile uint8_t*)
729#define IO_REG16 (volatile uint16_t*)
731#define IO_REG32 (volatile uint32_t*)
733#define IO_REG64 (volatile uint64_t*)
735#define IO_ROM8 (const volatile uint8_t*)
737#define IO_ROM16 (const volatile uint16_t*)
739#define IO_ROM32 (const volatile uint32_t*)
741#define IO_ROM64 (const volatile uint64_t*)
745/**********************************************************************/
750typedef struct __attribute__((packed,aligned(4))) {
751 uint32_t REG[32];
753
755#define NEORV32_CFS_BASE (0xFFFFFE00UL)
756
758#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (NEORV32_CFS_BASE)))
762/**********************************************************************/
767typedef struct __attribute__((packed,aligned(4))) {
768 uint32_t CTRL;
769 uint32_t DUTY[15];
771
773#define NEORV32_PWM_BASE (0xFFFFFE80UL)
774
776#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (NEORV32_PWM_BASE)))
777
783 PWM_CTRL_PRSC2 = 3
788/**********************************************************************/
793typedef struct __attribute__((packed,aligned(4))) {
794 uint32_t CTRL;
795 const uint32_t reserved0[3];
796 uint32_t STATUS;
797 const uint32_t reserved1[3];
798 uint32_t DATA[8];
800
802#define NEORV32_SLINK_BASE (0xFFFFFEC0UL)
803
805#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (NEORV32_SLINK_BASE)))
806
827
841};
845/**********************************************************************/
850typedef struct __attribute__((packed,aligned(4))) {
851 uint32_t CTRL;
852 const uint32_t reserved;
853 uint32_t DATA_LO;
854 uint32_t DATA_HI;
856
858#define NEORV32_XIP_BASE (0xFFFFFF40UL)
859
861#define NEORV32_XIP (*((volatile neorv32_xip_t*) (NEORV32_XIP_BASE)))
862
889/**********************************************************************/
894typedef struct __attribute__((packed,aligned(4))) {
895 uint32_t CTRL;
896 uint32_t THRES;
897 uint32_t COUNT;
898 const uint32_t reserved;
900
902#define NEORV32_GPTMR_BASE (0xFFFFFF60UL)
903
905#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (NEORV32_GPTMR_BASE)))
906
913 GPTMR_CTRL_MODE = 4
918/**********************************************************************/
923typedef struct __attribute__((packed,aligned(4))) {
924 uint32_t CTRL;
926
928#define NEORV32_BUSKEEPER_BASE (0xFFFFFF7CUL)
929
931#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE)))
932
941/**********************************************************************/
946typedef struct __attribute__((packed,aligned(4))) {
947 uint32_t IER;
948 uint32_t IPR;
949 uint32_t SCR;
950 const uint32_t reserved;
952
954#define NEORV32_XIRQ_BASE (0xFFFFFF80UL)
955
957#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (NEORV32_XIRQ_BASE)))
961/**********************************************************************/
966typedef struct __attribute__((packed,aligned(4))) {
967 uint32_t TIME_LO;
968 uint32_t TIME_HI;
969 uint32_t TIMECMP_LO;
970 uint32_t TIMECMP_HI;
972
974#define NEORV32_MTIME_BASE (0xFFFFFF90UL)
975
977#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (NEORV32_MTIME_BASE)))
981/**********************************************************************/
986typedef struct __attribute__((packed,aligned(4))) {
987 uint32_t CTRL;
988 uint32_t DATA;
990
992#define NEORV32_UART0_BASE (0xFFFFFFA0UL)
993
995#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (NEORV32_UART0_BASE)))
996
998typedef struct __attribute__((packed,aligned(4))) {
999 uint32_t CTRL;
1000 uint32_t DATA;
1002
1004#define NEORV32_UART1_BASE (0xFFFFFFD0UL)
1005
1007#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (NEORV32_UART1_BASE)))
1008
1042 UART_CTRL_TX_BUSY = 31
1044
1049 PARITY_ODD = 0b11
1051
1057 FLOW_CONTROL_RTSCTS = 0b11
1059
1068 UART_DATA_AVAIL = 31
1073/**********************************************************************/
1078typedef struct __attribute__((packed,aligned(4))) {
1079 uint32_t CTRL;
1080 uint32_t DATA;
1082
1084#define NEORV32_SPI_BASE (0xFFFFFFA8UL)
1085
1087#define NEORV32_SPI (*((volatile neorv32_spi_t*) (NEORV32_SPI_BASE)))
1088
1109 SPI_CTRL_BUSY = 31
1114/**********************************************************************/
1119typedef struct __attribute__((packed,aligned(4))) {
1120 uint32_t CTRL;
1121 uint32_t DATA;
1123
1125#define NEORV32_TWI_BASE (0xFFFFFFB0UL)
1126
1128#define NEORV32_TWI (*((volatile neorv32_twi_t*) (NEORV32_TWI_BASE)))
1129
1142 TWI_CTRL_BUSY = 31
1144
1148 TWI_DATA_MSB = 7
1153/**********************************************************************/
1158typedef struct __attribute__((packed,aligned(4))) {
1159 uint32_t CTRL;
1161
1163#define NEORV32_TRNG_BASE (0xFFFFFFB8UL)
1164
1166#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (NEORV32_TRNG_BASE)))
1167
1176 TRNG_CTRL_VALID = 31
1181/**********************************************************************/
1186typedef struct __attribute__((packed,aligned(4))) {
1187 uint32_t CTRL;
1189
1191#define NEORV32_WDT_BASE (0xFFFFFFBCUL)
1192
1194#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (NEORV32_WDT_BASE)))
1195
1197#define NEORV32_WDT_PWD (0xCA36)
1198
1215 WDT_CTRL_PWD_MSB = 31
1220/**********************************************************************/
1225typedef struct __attribute__((packed,aligned(4))) {
1226 const uint32_t INPUT_LO;
1227 const uint32_t INPUT_HI;
1228 uint32_t OUTPUT_LO;
1229 uint32_t OUTPUT_HI;
1231
1233#define NEORV32_GPIO_BASE (0xFFFFFFC0UL)
1234
1236#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (NEORV32_GPIO_BASE)))
1240/**********************************************************************/
1245typedef struct __attribute__((packed,aligned(4))) {
1246 uint32_t CTRL;
1247 uint32_t DATA;
1249
1251#define NEORV32_NEOLED_BASE (0xFFFFFFD8UL)
1252
1254#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (NEORV32_NEOLED_BASE)))
1255
1264 //
1269 //
1275 //
1281 //
1287 //
1297/**********************************************************************/
1302typedef struct __attribute__((packed,aligned(4))) {
1303 const uint32_t CLK;
1304 const uint32_t reserved;
1305 const uint32_t SOC;
1306 const uint32_t CACHE;
1307 const uint32_t ISPACE_BASE;
1308 const uint32_t DSPACE_BASE;
1309 const uint32_t IMEM_SIZE;
1310 const uint32_t DMEM_SIZE;
1312
1314#define NEORV32_SYSINFO_BASE (0xFFFFFFE0UL)
1315
1317#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE)))
1318
1346 SYSINFO_SOC_IO_XIP = 30
1348
1370};
1374// ----------------------------------------------------------------------------
1375// Include all system header files
1376// ----------------------------------------------------------------------------
1377// intrinsics
1378#include "neorv32_intrinsics.h"
1379
1380// cpu core
1381#include "neorv32_cpu.h"
1382#include "neorv32_cpu_cfu.h"
1383
1384// neorv32 runtime environment
1385#include "neorv32_rte.h"
1386
1387// io/peripheral devices
1388#include "neorv32_cfs.h"
1389#include "neorv32_gpio.h"
1390#include "neorv32_gptmr.h"
1391#include "neorv32_mtime.h"
1392#include "neorv32_neoled.h"
1393#include "neorv32_pwm.h"
1394#include "neorv32_slink.h"
1395#include "neorv32_spi.h"
1396#include "neorv32_trng.h"
1397#include "neorv32_twi.h"
1398#include "neorv32_uart.h"
1399#include "neorv32_wdt.h"
1400#include "neorv32_xip.h"
1401#include "neorv32_xirq.h"
1402
1403#ifdef __cplusplus
1404}
1405#endif
1406
1407#endif // neorv32_h
NEORV32_TWI_DATA_enum
Definition: neorv32.h:1146
@ TWI_DATA_MSB
Definition: neorv32.h:1148
@ TWI_DATA_LSB
Definition: neorv32.h:1147
NEORV32_WDT_CTRL_enum
Definition: neorv32.h:1200
@ WDT_CTRL_EN
Definition: neorv32.h:1201
@ WDT_CTRL_CLK_SEL0
Definition: neorv32.h:1202
@ WDT_CTRL_MODE
Definition: neorv32.h:1205
@ WDT_CTRL_PWD_MSB
Definition: neorv32.h:1215
@ WDT_CTRL_DBEN
Definition: neorv32.h:1210
@ WDT_CTRL_FORCE
Definition: neorv32.h:1208
@ WDT_CTRL_CLK_SEL1
Definition: neorv32.h:1203
@ WDT_CTRL_HALF
Definition: neorv32.h:1211
@ WDT_CTRL_PAUSE
Definition: neorv32.h:1212
@ WDT_CTRL_RESET
Definition: neorv32.h:1207
@ WDT_CTRL_CLK_SEL2
Definition: neorv32.h:1204
@ WDT_CTRL_PWD_LSB
Definition: neorv32.h:1214
@ WDT_CTRL_LOCK
Definition: neorv32.h:1209
@ WDT_CTRL_RCAUSE
Definition: neorv32.h:1206
NEORV32_CSR_MIE_enum
Definition: neorv32.h:376
@ CSR_MIE_FIRQ9E
Definition: neorv32.h:390
@ CSR_MIE_FIRQ13E
Definition: neorv32.h:394
@ CSR_MIE_FIRQ5E
Definition: neorv32.h:386
@ CSR_MIE_MTIE
Definition: neorv32.h:378
@ CSR_MIE_FIRQ8E
Definition: neorv32.h:389
@ CSR_MIE_FIRQ7E
Definition: neorv32.h:388
@ CSR_MIE_FIRQ12E
Definition: neorv32.h:393
@ CSR_MIE_FIRQ4E
Definition: neorv32.h:385
@ CSR_MIE_FIRQ3E
Definition: neorv32.h:384
@ CSR_MIE_FIRQ14E
Definition: neorv32.h:395
@ CSR_MIE_FIRQ6E
Definition: neorv32.h:387
@ CSR_MIE_FIRQ0E
Definition: neorv32.h:381
@ CSR_MIE_FIRQ15E
Definition: neorv32.h:396
@ CSR_MIE_FIRQ1E
Definition: neorv32.h:382
@ CSR_MIE_MEIE
Definition: neorv32.h:379
@ CSR_MIE_FIRQ11E
Definition: neorv32.h:392
@ CSR_MIE_FIRQ2E
Definition: neorv32.h:383
@ CSR_MIE_MSIE
Definition: neorv32.h:377
@ CSR_MIE_FIRQ10E
Definition: neorv32.h:391
NEORV32_CLOCK_PRSC_enum
Definition: neorv32.h:558
@ CLK_PRSC_4096
Definition: neorv32.h:566
@ CLK_PRSC_1024
Definition: neorv32.h:564
@ CLK_PRSC_64
Definition: neorv32.h:562
@ CLK_PRSC_4
Definition: neorv32.h:560
@ CLK_PRSC_128
Definition: neorv32.h:563
@ CLK_PRSC_2048
Definition: neorv32.h:565
@ CLK_PRSC_8
Definition: neorv32.h:561
@ CLK_PRSC_2
Definition: neorv32.h:559
NEORV32_GPTMR_CTRL_enum
Definition: neorv32.h:908
@ GPTMR_CTRL_PRSC2
Definition: neorv32.h:912
@ GPTMR_CTRL_PRSC1
Definition: neorv32.h:911
@ GPTMR_CTRL_MODE
Definition: neorv32.h:913
@ GPTMR_CTRL_EN
Definition: neorv32.h:909
@ GPTMR_CTRL_PRSC0
Definition: neorv32.h:910
NEORV32_TRNG_CTRL_enum
Definition: neorv32.h:1169
@ TRNG_CTRL_EN
Definition: neorv32.h:1175
@ TRNG_CTRL_VALID
Definition: neorv32.h:1176
@ TRNG_CTRL_DATA_LSB
Definition: neorv32.h:1170
@ TRNG_CTRL_DATA_MSB
Definition: neorv32.h:1171
@ TRNG_CTRL_SIM_MODE
Definition: neorv32.h:1174
@ TRNG_CTRL_FIFO_CLR
Definition: neorv32.h:1173
NEORV32_UART_FLOW_CONTROL_enum
Definition: neorv32.h:1053
@ FLOW_CONTROL_RTS
Definition: neorv32.h:1055
@ FLOW_CONTROL_CTS
Definition: neorv32.h:1056
@ FLOW_CONTROL_NONE
Definition: neorv32.h:1054
@ FLOW_CONTROL_RTSCTS
Definition: neorv32.h:1057
NEORV32_OCD_DM_SREG_enum
Definition: neorv32.h:706
@ OCD_DM_SREG_HALT_ACK
Definition: neorv32.h:707
@ OCD_DM_SREG_RESUME_ACK
Definition: neorv32.h:709
@ OCD_DM_SREG_RESUME_REQ
Definition: neorv32.h:708
@ OCD_DM_SREG_EXECUTE_REQ
Definition: neorv32.h:710
@ OCD_DM_SREG_EXCEPTION_ACK
Definition: neorv32.h:712
@ OCD_DM_SREG_EXECUTE_ACK
Definition: neorv32.h:711
NEORV32_SYSINFO_CACHE_enum
Definition: neorv32.h:1350
@ SYSINFO_CACHE_IC_REPLACEMENT_3
Definition: neorv32.h:1369
@ SYSINFO_CACHE_IC_REPLACEMENT_1
Definition: neorv32.h:1367
@ SYSINFO_CACHE_IC_NUM_BLOCKS_2
Definition: neorv32.h:1358
@ SYSINFO_CACHE_IC_BLOCK_SIZE_1
Definition: neorv32.h:1352
@ SYSINFO_CACHE_IC_NUM_BLOCKS_1
Definition: neorv32.h:1357
@ SYSINFO_CACHE_IC_ASSOCIATIVITY_3
Definition: neorv32.h:1364
@ SYSINFO_CACHE_IC_BLOCK_SIZE_3
Definition: neorv32.h:1354
@ SYSINFO_CACHE_IC_NUM_BLOCKS_3
Definition: neorv32.h:1359
@ SYSINFO_CACHE_IC_ASSOCIATIVITY_2
Definition: neorv32.h:1363
@ SYSINFO_CACHE_IC_BLOCK_SIZE_2
Definition: neorv32.h:1353
@ SYSINFO_CACHE_IC_NUM_BLOCKS_0
Definition: neorv32.h:1356
@ SYSINFO_CACHE_IC_REPLACEMENT_0
Definition: neorv32.h:1366
@ SYSINFO_CACHE_IC_ASSOCIATIVITY_1
Definition: neorv32.h:1362
@ SYSINFO_CACHE_IC_ASSOCIATIVITY_0
Definition: neorv32.h:1361
@ SYSINFO_CACHE_IC_REPLACEMENT_2
Definition: neorv32.h:1368
@ SYSINFO_CACHE_IC_BLOCK_SIZE_0
Definition: neorv32.h:1351
NEORV32_HPMCNT_EVENT_enum
Definition: neorv32.h:477
@ HPMCNT_EVENT_LOAD
Definition: neorv32.h:485
@ HPMCNT_EVENT_CY
Definition: neorv32.h:478
@ HPMCNT_EVENT_TRAP
Definition: neorv32.h:493
@ HPMCNT_EVENT_STORE
Definition: neorv32.h:486
@ HPMCNT_EVENT_WAIT_LS
Definition: neorv32.h:487
@ HPMCNT_EVENT_WAIT_MC
Definition: neorv32.h:484
@ HPMCNT_EVENT_TBRANCH
Definition: neorv32.h:491
@ HPMCNT_EVENT_WAIT_IF
Definition: neorv32.h:482
@ HPMCNT_EVENT_BRANCH
Definition: neorv32.h:490
@ HPMCNT_EVENT_IR
Definition: neorv32.h:479
@ HPMCNT_EVENT_ILLEGAL
Definition: neorv32.h:494
@ HPMCNT_EVENT_JUMP
Definition: neorv32.h:489
@ HPMCNT_EVENT_CIR
Definition: neorv32.h:481
@ HPMCNT_EVENT_WAIT_II
Definition: neorv32.h:483
NEORV32_CSR_MIP_enum
Definition: neorv32.h:403
@ CSR_MIP_FIRQ12P
Definition: neorv32.h:421
@ CSR_MIP_FIRQ15P
Definition: neorv32.h:424
@ CSR_MIP_MSIP
Definition: neorv32.h:404
@ CSR_MIP_FIRQ13P
Definition: neorv32.h:422
@ CSR_MIP_MEIP
Definition: neorv32.h:406
@ CSR_MIP_FIRQ0P
Definition: neorv32.h:409
@ CSR_MIP_FIRQ10P
Definition: neorv32.h:419
@ CSR_MIP_FIRQ1P
Definition: neorv32.h:410
@ CSR_MIP_MTIP
Definition: neorv32.h:405
@ CSR_MIP_FIRQ11P
Definition: neorv32.h:420
@ CSR_MIP_FIRQ3P
Definition: neorv32.h:412
@ CSR_MIP_FIRQ5P
Definition: neorv32.h:414
@ CSR_MIP_FIRQ14P
Definition: neorv32.h:423
@ CSR_MIP_FIRQ7P
Definition: neorv32.h:416
@ CSR_MIP_FIRQ4P
Definition: neorv32.h:413
@ CSR_MIP_FIRQ9P
Definition: neorv32.h:418
@ CSR_MIP_FIRQ2P
Definition: neorv32.h:411
@ CSR_MIP_FIRQ8P
Definition: neorv32.h:417
@ CSR_MIP_FIRQ6P
Definition: neorv32.h:415
NEORV32_CSR_MCOUNTEREN_enum
Definition: neorv32.h:327
@ CSR_MCOUNTEREN_CY
Definition: neorv32.h:328
@ CSR_MCOUNTEREN_IR
Definition: neorv32.h:330
@ CSR_MCOUNTEREN_TM
Definition: neorv32.h:329
NEORV32_TWI_CTRL_enum
Definition: neorv32.h:1131
@ TWI_CTRL_STOP
Definition: neorv32.h:1134
@ TWI_CTRL_EN
Definition: neorv32.h:1132
@ TWI_CTRL_BUSY
Definition: neorv32.h:1142
@ TWI_CTRL_PRSC2
Definition: neorv32.h:1137
@ TWI_CTRL_CLAIMED
Definition: neorv32.h:1140
@ TWI_CTRL_PRSC1
Definition: neorv32.h:1136
@ TWI_CTRL_PRSC0
Definition: neorv32.h:1135
@ TWI_CTRL_ACK
Definition: neorv32.h:1141
@ TWI_CTRL_MACK
Definition: neorv32.h:1138
@ TWI_CTRL_START
Definition: neorv32.h:1133
NEORV32_XIP_CTRL_enum
Definition: neorv32.h:864
@ XIP_CTRL_SPI_NBYTES_LSB
Definition: neorv32.h:871
@ XIP_CTRL_EN
Definition: neorv32.h:865
@ XIP_CTRL_XIP_BUSY
Definition: neorv32.h:884
@ XIP_CTRL_RD_CMD_MSB
Definition: neorv32.h:877
@ XIP_CTRL_XIP_EN
Definition: neorv32.h:873
@ XIP_CTRL_XIP_ABYTES_MSB
Definition: neorv32.h:875
@ XIP_CTRL_SPI_CSEN
Definition: neorv32.h:880
@ XIP_CTRL_SPI_NBYTES_MSB
Definition: neorv32.h:872
@ XIP_CTRL_PAGE_MSB
Definition: neorv32.h:879
@ XIP_CTRL_XIP_ABYTES_LSB
Definition: neorv32.h:874
@ XIP_CTRL_PRSC0
Definition: neorv32.h:866
@ XIP_CTRL_PHY_BUSY
Definition: neorv32.h:883
@ XIP_CTRL_RD_CMD_LSB
Definition: neorv32.h:876
@ XIP_CTRL_PRSC2
Definition: neorv32.h:868
@ XIP_CTRL_CPOL
Definition: neorv32.h:869
@ XIP_CTRL_HIGHSPEED
Definition: neorv32.h:881
@ XIP_CTRL_CPHA
Definition: neorv32.h:870
@ XIP_CTRL_PRSC1
Definition: neorv32.h:867
@ XIP_CTRL_PAGE_LSB
Definition: neorv32.h:878
NEORV32_CSR_MSTATUS_enum
Definition: neorv32.h:315
@ CSR_MSTATUS_MPP_H
Definition: neorv32.h:319
@ CSR_MSTATUS_MPIE
Definition: neorv32.h:317
@ CSR_MSTATUS_TW
Definition: neorv32.h:320
@ CSR_MSTATUS_MIE
Definition: neorv32.h:316
@ CSR_MSTATUS_MPP_L
Definition: neorv32.h:318
NEORV32_SLINK_STATUS_enum
Definition: neorv32.h:829
@ SLINK_STATUS_TX_LAST_LSB
Definition: neorv32.h:839
@ SLINK_STATUS_RX_AVAIL_LSB
Definition: neorv32.h:830
@ SLINK_STATUS_TX_LAST_MSB
Definition: neorv32.h:840
@ SLINK_STATUS_RX_LAST_MSB
Definition: neorv32.h:837
@ SLINK_STATUS_TX_FREE_MSB
Definition: neorv32.h:834
@ SLINK_STATUS_RX_LAST_LSB
Definition: neorv32.h:836
@ SLINK_STATUS_TX_FREE_LSB
Definition: neorv32.h:833
@ SLINK_STATUS_RX_AVAIL_MSB
Definition: neorv32.h:831
NEORV32_PMP_MODES_enum
Definition: neorv32.h:513
@ PMP_OFF
Definition: neorv32.h:514
@ PMP_TOR
Definition: neorv32.h:515
NEORV32_CSR_MCOUNTINHIBIT_enum
Definition: neorv32.h:337
@ CSR_MCOUNTINHIBIT_HPM15
Definition: neorv32.h:353
@ CSR_MCOUNTINHIBIT_HPM9
Definition: neorv32.h:347
@ CSR_MCOUNTINHIBIT_HPM30
Definition: neorv32.h:368
@ CSR_MCOUNTINHIBIT_HPM26
Definition: neorv32.h:364
@ CSR_MCOUNTINHIBIT_HPM31
Definition: neorv32.h:369
@ CSR_MCOUNTINHIBIT_HPM21
Definition: neorv32.h:359
@ CSR_MCOUNTINHIBIT_CY
Definition: neorv32.h:338
@ CSR_MCOUNTINHIBIT_HPM5
Definition: neorv32.h:343
@ CSR_MCOUNTINHIBIT_HPM28
Definition: neorv32.h:366
@ CSR_MCOUNTINHIBIT_HPM19
Definition: neorv32.h:357
@ CSR_MCOUNTINHIBIT_HPM7
Definition: neorv32.h:345
@ CSR_MCOUNTINHIBIT_HPM4
Definition: neorv32.h:342
@ CSR_MCOUNTINHIBIT_HPM27
Definition: neorv32.h:365
@ CSR_MCOUNTINHIBIT_IR
Definition: neorv32.h:339
@ CSR_MCOUNTINHIBIT_HPM16
Definition: neorv32.h:354
@ CSR_MCOUNTINHIBIT_HPM24
Definition: neorv32.h:362
@ CSR_MCOUNTINHIBIT_HPM23
Definition: neorv32.h:361
@ CSR_MCOUNTINHIBIT_HPM17
Definition: neorv32.h:355
@ CSR_MCOUNTINHIBIT_HPM12
Definition: neorv32.h:350
@ CSR_MCOUNTINHIBIT_HPM10
Definition: neorv32.h:348
@ CSR_MCOUNTINHIBIT_HPM29
Definition: neorv32.h:367
@ CSR_MCOUNTINHIBIT_HPM18
Definition: neorv32.h:356
@ CSR_MCOUNTINHIBIT_HPM14
Definition: neorv32.h:352
@ CSR_MCOUNTINHIBIT_HPM8
Definition: neorv32.h:346
@ CSR_MCOUNTINHIBIT_HPM11
Definition: neorv32.h:349
@ CSR_MCOUNTINHIBIT_HPM6
Definition: neorv32.h:344
@ CSR_MCOUNTINHIBIT_HPM13
Definition: neorv32.h:351
@ CSR_MCOUNTINHIBIT_HPM20
Definition: neorv32.h:358
@ CSR_MCOUNTINHIBIT_HPM25
Definition: neorv32.h:363
@ CSR_MCOUNTINHIBIT_HPM22
Definition: neorv32.h:360
@ CSR_MCOUNTINHIBIT_HPM3
Definition: neorv32.h:341
NEORV32_NEOLED_CTRL_enum
Definition: neorv32.h:1257
@ NEOLED_CTRL_T_ONE_H_4
Definition: neorv32.h:1286
@ NEOLED_CTRL_T_ZERO_H_4
Definition: neorv32.h:1280
@ NEOLED_CTRL_PRSC1
Definition: neorv32.h:1262
@ NEOLED_CTRL_PRSC0
Definition: neorv32.h:1261
@ NEOLED_CTRL_TX_HALF
Definition: neorv32.h:1290
@ NEOLED_CTRL_T_ZERO_H_1
Definition: neorv32.h:1277
@ NEOLED_CTRL_TX_EMPTY
Definition: neorv32.h:1289
@ NEOLED_CTRL_T_ONE_H_3
Definition: neorv32.h:1285
@ NEOLED_CTRL_IRQ_CONF
Definition: neorv32.h:1288
@ NEOLED_CTRL_BUFS_0
Definition: neorv32.h:1265
@ NEOLED_CTRL_PRSC2
Definition: neorv32.h:1263
@ NEOLED_CTRL_T_TOT_4
Definition: neorv32.h:1274
@ NEOLED_CTRL_T_TOT_2
Definition: neorv32.h:1272
@ NEOLED_CTRL_STROBE
Definition: neorv32.h:1260
@ NEOLED_CTRL_T_TOT_0
Definition: neorv32.h:1270
@ NEOLED_CTRL_T_ONE_H_2
Definition: neorv32.h:1284
@ NEOLED_CTRL_TX_BUSY
Definition: neorv32.h:1292
@ NEOLED_CTRL_T_ZERO_H_0
Definition: neorv32.h:1276
@ NEOLED_CTRL_T_ONE_H_0
Definition: neorv32.h:1282
@ NEOLED_CTRL_T_ZERO_H_2
Definition: neorv32.h:1278
@ NEOLED_CTRL_T_ZERO_H_3
Definition: neorv32.h:1279
@ NEOLED_CTRL_MODE
Definition: neorv32.h:1259
@ NEOLED_CTRL_BUFS_3
Definition: neorv32.h:1268
@ NEOLED_CTRL_T_TOT_3
Definition: neorv32.h:1273
@ NEOLED_CTRL_TX_FULL
Definition: neorv32.h:1291
@ NEOLED_CTRL_T_TOT_1
Definition: neorv32.h:1271
@ NEOLED_CTRL_BUFS_2
Definition: neorv32.h:1267
@ NEOLED_CTRL_T_ONE_H_1
Definition: neorv32.h:1283
@ NEOLED_CTRL_BUFS_1
Definition: neorv32.h:1266
@ NEOLED_CTRL_EN
Definition: neorv32.h:1258
NEORV32_PMPCFG_ATTRIBUTES_enum
Definition: neorv32.h:501
@ PMPCFG_L
Definition: neorv32.h:507
@ PMPCFG_A_MSB
Definition: neorv32.h:506
@ PMPCFG_W
Definition: neorv32.h:503
@ PMPCFG_A_LSB
Definition: neorv32.h:505
@ PMPCFG_R
Definition: neorv32.h:502
@ PMPCFG_X
Definition: neorv32.h:504
NEORV32_SLINK_CTRL_enum
Definition: neorv32.h:808
@ SLINK_CTRL_TX_FIFO_S0
Definition: neorv32.h:816
@ SLINK_CTRL_RX_IRQ_EN_LSB
Definition: neorv32.h:821
@ SLINK_CTRL_RX_FIFO_S3
Definition: neorv32.h:814
@ SLINK_CTRL_TX_FIFO_S3
Definition: neorv32.h:819
@ SLINK_CTRL_TX_FIFO_S1
Definition: neorv32.h:817
@ SLINK_CTRL_EN
Definition: neorv32.h:809
@ SLINK_CTRL_RX_FIFO_S0
Definition: neorv32.h:811
@ SLINK_CTRL_TX_FIFO_S2
Definition: neorv32.h:818
@ SLINK_CTRL_RX_IRQ_EN_MSB
Definition: neorv32.h:822
@ SLINK_CTRL_RX_FIFO_S1
Definition: neorv32.h:812
@ SLINK_CTRL_RX_FIFO_S2
Definition: neorv32.h:813
@ SLINK_CTRL_TX_IRQ_EN_LSB
Definition: neorv32.h:824
@ SLINK_CTRL_TX_IRQ_EN_MSB
Definition: neorv32.h:825
NEORV32_CSR_enum
Definition: neorv32.h:62
@ CSR_MHPMCOUNTER23
Definition: neorv32.h:186
@ CSR_MCONFIGPTR
Definition: neorv32.h:306
@ CSR_PMPCFG3
Definition: neorv32.h:128
@ CSR_MIMPID
Definition: neorv32.h:304
@ CSR_MHPMEVENT15
Definition: neorv32.h:99
@ CSR_MHPMEVENT16
Definition: neorv32.h:100
@ CSR_PMPCFG2
Definition: neorv32.h:127
@ CSR_MHPMCOUNTER26
Definition: neorv32.h:189
@ CSR_MHPMCOUNTER22
Definition: neorv32.h:185
@ CSR_MHPMCOUNTER27
Definition: neorv32.h:190
@ CSR_MHPMCOUNTER18H
Definition: neorv32.h:214
@ CSR_MHPMCOUNTER12
Definition: neorv32.h:175
@ CSR_MCOUNTEREN
Definition: neorv32.h:76
@ CSR_MHPMCOUNTER9
Definition: neorv32.h:172
@ CSR_SCONTEXT
Definition: neorv32.h:155
@ CSR_MHPMEVENT6
Definition: neorv32.h:90
@ CSR_MHPMCOUNTER10H
Definition: neorv32.h:206
@ CSR_MHPMCOUNTER15
Definition: neorv32.h:178
@ CSR_PMPCFG1
Definition: neorv32.h:126
@ CSR_PMPADDR12
Definition: neorv32.h:142
@ CSR_MHPMEVENT10
Definition: neorv32.h:94
@ CSR_MHPMEVENT5
Definition: neorv32.h:89
@ CSR_MHPMCOUNTER3H
Definition: neorv32.h:199
@ CSR_MCYCLEH
Definition: neorv32.h:196
@ CSR_MCAUSE
Definition: neorv32.h:120
@ CSR_MHPMEVENT7
Definition: neorv32.h:91
@ CSR_MHPMCOUNTER4H
Definition: neorv32.h:200
@ CSR_PMPADDR13
Definition: neorv32.h:143
@ CSR_MCYCLE
Definition: neorv32.h:163
@ CSR_MHPMCOUNTER12H
Definition: neorv32.h:208
@ CSR_MHPMCOUNTER30H
Definition: neorv32.h:226
@ CSR_MXISA
Definition: neorv32.h:308
@ CSR_MHPMCOUNTER27H
Definition: neorv32.h:223
@ CSR_MHPMEVENT31
Definition: neorv32.h:115
@ CSR_MHPMCOUNTER21
Definition: neorv32.h:184
@ CSR_MHPMCOUNTER25H
Definition: neorv32.h:221
@ CSR_MCOUNTINHIBIT
Definition: neorv32.h:84
@ CSR_MHPMEVENT23
Definition: neorv32.h:107
@ CSR_PMPADDR11
Definition: neorv32.h:141
@ CSR_MHPMEVENT18
Definition: neorv32.h:102
@ CSR_MHPMCOUNTER24
Definition: neorv32.h:187
@ CSR_MENVCFGH
Definition: neorv32.h:82
@ CSR_MHPMCOUNTER6H
Definition: neorv32.h:202
@ CSR_MHPMEVENT3
Definition: neorv32.h:87
@ CSR_MHPMCOUNTER23H
Definition: neorv32.h:219
@ CSR_MHPMCOUNTER20
Definition: neorv32.h:183
@ CSR_MHPMEVENT21
Definition: neorv32.h:105
@ CSR_PMPADDR9
Definition: neorv32.h:139
@ CSR_MHPMCOUNTER10
Definition: neorv32.h:173
@ CSR_MHPMCOUNTER8
Definition: neorv32.h:171
@ CSR_MCONTEXT
Definition: neorv32.h:154
@ CSR_MHPMCOUNTER29
Definition: neorv32.h:192
@ CSR_MEPC
Definition: neorv32.h:119
@ CSR_MHPMCOUNTER13H
Definition: neorv32.h:209
@ CSR_FCSR
Definition: neorv32.h:69
@ CSR_FFLAGS
Definition: neorv32.h:67
@ CSR_MHPMCOUNTER31H
Definition: neorv32.h:227
@ CSR_PMPADDR15
Definition: neorv32.h:145
@ CSR_TDATA3
Definition: neorv32.h:151
@ CSR_MHPMEVENT24
Definition: neorv32.h:108
@ CSR_PMPADDR1
Definition: neorv32.h:131
@ CSR_MHARTID
Definition: neorv32.h:305
@ CSR_MHPMEVENT20
Definition: neorv32.h:104
@ CSR_MHPMCOUNTER16H
Definition: neorv32.h:212
@ CSR_MHPMCOUNTER20H
Definition: neorv32.h:216
@ CSR_MHPMCOUNTER9H
Definition: neorv32.h:205
@ CSR_MHPMCOUNTER5H
Definition: neorv32.h:201
@ CSR_MTVAL
Definition: neorv32.h:121
@ CSR_MHPMCOUNTER19
Definition: neorv32.h:182
@ CSR_MHPMCOUNTER30
Definition: neorv32.h:193
@ CSR_MHPMCOUNTER28H
Definition: neorv32.h:224
@ CSR_MHPMEVENT26
Definition: neorv32.h:110
@ CSR_FRM
Definition: neorv32.h:68
@ CSR_MHPMEVENT11
Definition: neorv32.h:95
@ CSR_MHPMCOUNTER11H
Definition: neorv32.h:207
@ CSR_TDATA1
Definition: neorv32.h:149
@ CSR_INSTRET
Definition: neorv32.h:231
@ CSR_MHPMCOUNTER11
Definition: neorv32.h:174
@ CSR_PMPADDR0
Definition: neorv32.h:130
@ CSR_PMPADDR3
Definition: neorv32.h:133
@ CSR_MHPMCOUNTER24H
Definition: neorv32.h:220
@ CSR_MHPMCOUNTER29H
Definition: neorv32.h:225
@ CSR_MHPMEVENT13
Definition: neorv32.h:97
@ CSR_MHPMCOUNTER21H
Definition: neorv32.h:217
@ CSR_MHPMCOUNTER17H
Definition: neorv32.h:213
@ CSR_MHPMCOUNTER28
Definition: neorv32.h:191
@ CSR_TCONTROL
Definition: neorv32.h:153
@ CSR_MHPMCOUNTER7
Definition: neorv32.h:170
@ CSR_PMPADDR14
Definition: neorv32.h:144
@ CSR_MHPMEVENT14
Definition: neorv32.h:98
@ CSR_MINSTRET
Definition: neorv32.h:164
@ CSR_INSTRETH
Definition: neorv32.h:268
@ CSR_MHPMCOUNTER4
Definition: neorv32.h:167
@ CSR_MHPMCOUNTER13
Definition: neorv32.h:176
@ CSR_MHPMEVENT22
Definition: neorv32.h:106
@ CSR_MENVCFG
Definition: neorv32.h:78
@ CSR_MHPMEVENT27
Definition: neorv32.h:111
@ CSR_MHPMCOUNTER8H
Definition: neorv32.h:204
@ CSR_PMPADDR2
Definition: neorv32.h:132
@ CSR_CYCLEH
Definition: neorv32.h:266
@ CSR_MTVEC
Definition: neorv32.h:75
@ CSR_TSELECT
Definition: neorv32.h:148
@ CSR_CYCLE
Definition: neorv32.h:229
@ CSR_TIME
Definition: neorv32.h:230
@ CSR_MHPMCOUNTER18
Definition: neorv32.h:181
@ CSR_MHPMEVENT4
Definition: neorv32.h:88
@ CSR_MHPMCOUNTER19H
Definition: neorv32.h:215
@ CSR_MHPMCOUNTER7H
Definition: neorv32.h:203
@ CSR_MSTATUSH
Definition: neorv32.h:80
@ CSR_MHPMCOUNTER25
Definition: neorv32.h:188
@ CSR_MHPMCOUNTER22H
Definition: neorv32.h:218
@ CSR_TIMEH
Definition: neorv32.h:267
@ CSR_MHPMCOUNTER14H
Definition: neorv32.h:210
@ CSR_MHPMEVENT17
Definition: neorv32.h:101
@ CSR_MHPMCOUNTER17
Definition: neorv32.h:180
@ CSR_MIE
Definition: neorv32.h:74
@ CSR_MHPMEVENT25
Definition: neorv32.h:109
@ CSR_PMPADDR4
Definition: neorv32.h:134
@ CSR_MHPMCOUNTER31
Definition: neorv32.h:194
@ CSR_TDATA2
Definition: neorv32.h:150
@ CSR_MSTATUS
Definition: neorv32.h:72
@ CSR_MHPMEVENT19
Definition: neorv32.h:103
@ CSR_MHPMEVENT8
Definition: neorv32.h:92
@ CSR_MHPMEVENT12
Definition: neorv32.h:96
@ CSR_MARCHID
Definition: neorv32.h:303
@ CSR_PMPADDR10
Definition: neorv32.h:140
@ CSR_PMPADDR5
Definition: neorv32.h:135
@ CSR_MHPMCOUNTER14
Definition: neorv32.h:177
@ CSR_MHPMEVENT28
Definition: neorv32.h:112
@ CSR_MIP
Definition: neorv32.h:122
@ CSR_MISA
Definition: neorv32.h:73
@ CSR_MHPMCOUNTER3
Definition: neorv32.h:166
@ CSR_MHPMCOUNTER26H
Definition: neorv32.h:222
@ CSR_MSCRATCH
Definition: neorv32.h:118
@ CSR_MHPMEVENT30
Definition: neorv32.h:114
@ CSR_PMPADDR7
Definition: neorv32.h:137
@ CSR_PMPADDR8
Definition: neorv32.h:138
@ CSR_MHPMCOUNTER16
Definition: neorv32.h:179
@ CSR_MHPMCOUNTER5
Definition: neorv32.h:168
@ CSR_PMPCFG0
Definition: neorv32.h:125
@ CSR_PMPADDR6
Definition: neorv32.h:136
@ CSR_MVENDORID
Definition: neorv32.h:302
@ CSR_MHPMCOUNTER15H
Definition: neorv32.h:211
@ CSR_MHPMCOUNTER6
Definition: neorv32.h:169
@ CSR_MHPMEVENT9
Definition: neorv32.h:93
@ CSR_TINFO
Definition: neorv32.h:152
@ CSR_MHPMEVENT29
Definition: neorv32.h:113
@ CSR_MINSTRETH
Definition: neorv32.h:197
NEORV32_BUSKEEPER_CTRL_enum
Definition: neorv32.h:934
@ BUSKEEPER_ERR_TYPE
Definition: neorv32.h:935
@ BUSKEEPER_ERR_FLAG
Definition: neorv32.h:936
NEORV32_EXCEPTION_CODES_enum
Definition: neorv32.h:522
@ TRAP_CODE_I_MISALIGNED
Definition: neorv32.h:523
@ TRAP_CODE_FIRQ_0
Definition: neorv32.h:536
@ TRAP_CODE_FIRQ_12
Definition: neorv32.h:548
@ TRAP_CODE_MTI
Definition: neorv32.h:534
@ TRAP_CODE_S_MISALIGNED
Definition: neorv32.h:529
@ TRAP_CODE_MEI
Definition: neorv32.h:535
@ TRAP_CODE_MENV_CALL
Definition: neorv32.h:532
@ TRAP_CODE_L_ACCESS
Definition: neorv32.h:528
@ TRAP_CODE_BREAKPOINT
Definition: neorv32.h:526
@ TRAP_CODE_FIRQ_9
Definition: neorv32.h:545
@ TRAP_CODE_FIRQ_3
Definition: neorv32.h:539
@ TRAP_CODE_FIRQ_10
Definition: neorv32.h:546
@ TRAP_CODE_FIRQ_5
Definition: neorv32.h:541
@ TRAP_CODE_L_MISALIGNED
Definition: neorv32.h:527
@ TRAP_CODE_I_ACCESS
Definition: neorv32.h:524
@ TRAP_CODE_S_ACCESS
Definition: neorv32.h:530
@ TRAP_CODE_FIRQ_13
Definition: neorv32.h:549
@ TRAP_CODE_FIRQ_6
Definition: neorv32.h:542
@ TRAP_CODE_FIRQ_14
Definition: neorv32.h:550
@ TRAP_CODE_FIRQ_11
Definition: neorv32.h:547
@ TRAP_CODE_UENV_CALL
Definition: neorv32.h:531
@ TRAP_CODE_FIRQ_15
Definition: neorv32.h:551
@ TRAP_CODE_FIRQ_4
Definition: neorv32.h:540
@ TRAP_CODE_FIRQ_8
Definition: neorv32.h:544
@ TRAP_CODE_FIRQ_2
Definition: neorv32.h:538
@ TRAP_CODE_FIRQ_1
Definition: neorv32.h:537
@ TRAP_CODE_MSI
Definition: neorv32.h:533
@ TRAP_CODE_FIRQ_7
Definition: neorv32.h:543
@ TRAP_CODE_I_ILLEGAL
Definition: neorv32.h:525
NEORV32_UART_CTRL_enum
Definition: neorv32.h:1010
@ UART_CTRL_BAUD08
Definition: neorv32.h:1019
@ UART_CTRL_TX_BUSY
Definition: neorv32.h:1042
@ UART_CTRL_PRSC0
Definition: neorv32.h:1035
@ UART_CTRL_BAUD03
Definition: neorv32.h:1014
@ UART_CTRL_BAUD11
Definition: neorv32.h:1022
@ UART_CTRL_TX_FULL
Definition: neorv32.h:1029
@ UART_CTRL_BAUD02
Definition: neorv32.h:1013
@ UART_CTRL_EN
Definition: neorv32.h:1039
@ UART_CTRL_RX_HALF
Definition: neorv32.h:1025
@ UART_CTRL_SIM_MODE
Definition: neorv32.h:1023
@ UART_CTRL_RX_FULL
Definition: neorv32.h:1026
@ UART_CTRL_PMODE1
Definition: neorv32.h:1034
@ UART_CTRL_BAUD07
Definition: neorv32.h:1018
@ UART_CTRL_RTS_EN
Definition: neorv32.h:1031
@ UART_CTRL_TX_HALF
Definition: neorv32.h:1028
@ UART_CTRL_PRSC2
Definition: neorv32.h:1037
@ UART_CTRL_TX_IRQ
Definition: neorv32.h:1041
@ UART_CTRL_BAUD05
Definition: neorv32.h:1016
@ UART_CTRL_BAUD04
Definition: neorv32.h:1015
@ UART_CTRL_PRSC1
Definition: neorv32.h:1036
@ UART_CTRL_BAUD06
Definition: neorv32.h:1017
@ UART_CTRL_BAUD10
Definition: neorv32.h:1021
@ UART_CTRL_CTS
Definition: neorv32.h:1038
@ UART_CTRL_CTS_EN
Definition: neorv32.h:1032
@ UART_CTRL_TX_EMPTY
Definition: neorv32.h:1027
@ UART_CTRL_BAUD00
Definition: neorv32.h:1011
@ UART_CTRL_PMODE0
Definition: neorv32.h:1033
@ UART_CTRL_RX_IRQ
Definition: neorv32.h:1040
@ UART_CTRL_RX_EMPTY
Definition: neorv32.h:1024
@ UART_CTRL_BAUD01
Definition: neorv32.h:1012
@ UART_CTRL_BAUD09
Definition: neorv32.h:1020
NEORV32_UART_DATA_enum
Definition: neorv32.h:1061
@ UART_DATA_MSB
Definition: neorv32.h:1063
@ UART_DATA_OVERR
Definition: neorv32.h:1067
@ UART_DATA_FERR
Definition: neorv32.h:1066
@ UART_DATA_LSB
Definition: neorv32.h:1062
@ UART_DATA_AVAIL
Definition: neorv32.h:1068
@ UART_DATA_PERR
Definition: neorv32.h:1065
NEORV32_SPI_CTRL_enum
Definition: neorv32.h:1090
@ SPI_CTRL_CS2
Definition: neorv32.h:1093
@ SPI_CTRL_SIZE0
Definition: neorv32.h:1104
@ SPI_CTRL_CS4
Definition: neorv32.h:1095
@ SPI_CTRL_CS0
Definition: neorv32.h:1091
@ SPI_CTRL_SIZE1
Definition: neorv32.h:1105
@ SPI_CTRL_CS5
Definition: neorv32.h:1096
@ SPI_CTRL_PRSC1
Definition: neorv32.h:1102
@ SPI_CTRL_CPHA
Definition: neorv32.h:1100
@ SPI_CTRL_EN
Definition: neorv32.h:1099
@ SPI_CTRL_CPOL
Definition: neorv32.h:1106
@ SPI_CTRL_BUSY
Definition: neorv32.h:1109
@ SPI_CTRL_PRSC2
Definition: neorv32.h:1103
@ SPI_CTRL_CS7
Definition: neorv32.h:1098
@ SPI_CTRL_CS1
Definition: neorv32.h:1092
@ SPI_CTRL_PRSC0
Definition: neorv32.h:1101
@ SPI_CTRL_HIGHSPEED
Definition: neorv32.h:1107
@ SPI_CTRL_CS6
Definition: neorv32.h:1097
@ SPI_CTRL_CS3
Definition: neorv32.h:1094
NEORV32_SYSINFO_SOC_enum
Definition: neorv32.h:1320
@ SYSINFO_SOC_ICACHE
Definition: neorv32.h:1326
@ SYSINFO_SOC_HW_RESET
Definition: neorv32.h:1330
@ SYSINFO_SOC_IO_NEOLED
Definition: neorv32.h:1343
@ SYSINFO_SOC_IO_TWI
Definition: neorv32.h:1336
@ SYSINFO_SOC_MEM_INT_IMEM
Definition: neorv32.h:1323
@ SYSINFO_SOC_IO_UART0
Definition: neorv32.h:1334
@ SYSINFO_SOC_IO_SLINK
Definition: neorv32.h:1341
@ SYSINFO_SOC_OCD
Definition: neorv32.h:1329
@ SYSINFO_SOC_IO_TRNG
Definition: neorv32.h:1340
@ SYSINFO_SOC_IO_GPTMR
Definition: neorv32.h:1345
@ SYSINFO_SOC_IO_SPI
Definition: neorv32.h:1335
@ SYSINFO_SOC_IO_UART1
Definition: neorv32.h:1342
@ SYSINFO_SOC_IO_MTIME
Definition: neorv32.h:1333
@ SYSINFO_SOC_MEM_INT_DMEM
Definition: neorv32.h:1324
@ SYSINFO_SOC_IO_GPIO
Definition: neorv32.h:1332
@ SYSINFO_SOC_BOOTLOADER
Definition: neorv32.h:1321
@ SYSINFO_SOC_MEM_EXT_ENDIAN
Definition: neorv32.h:1325
@ SYSINFO_SOC_IO_XIP
Definition: neorv32.h:1346
@ SYSINFO_SOC_IO_PWM
Definition: neorv32.h:1337
@ SYSINFO_SOC_IO_XIRQ
Definition: neorv32.h:1344
@ SYSINFO_SOC_MEM_EXT
Definition: neorv32.h:1322
@ SYSINFO_SOC_IO_CFS
Definition: neorv32.h:1339
@ SYSINFO_SOC_IS_SIM
Definition: neorv32.h:1328
@ SYSINFO_SOC_IO_WDT
Definition: neorv32.h:1338
NEORV32_CSR_XISA_enum
Definition: neorv32.h:450
@ CSR_MXISA_ZXSCNT
Definition: neorv32.h:458
@ CSR_MXISA_ZICNTR
Definition: neorv32.h:459
@ CSR_MXISA_FASTMUL
Definition: neorv32.h:469
@ CSR_MXISA_ZFINX
Definition: neorv32.h:457
@ CSR_MXISA_ZIFENCEI
Definition: neorv32.h:453
@ CSR_MXISA_ZMMUL
Definition: neorv32.h:454
@ CSR_MXISA_IS_SIM
Definition: neorv32.h:465
@ CSR_MXISA_HW_RESET
Definition: neorv32.h:466
@ CSR_MXISA_ZIHPM
Definition: neorv32.h:461
@ CSR_MXISA_PMP
Definition: neorv32.h:460
@ CSR_MXISA_DEBUGMODE
Definition: neorv32.h:462
@ CSR_MXISA_ZICSR
Definition: neorv32.h:452
@ CSR_MXISA_FASTSHIFT
Definition: neorv32.h:470
@ CSR_MXISA_ZXCFU
Definition: neorv32.h:455
NEORV32_PWM_CTRL_enum
Definition: neorv32.h:779
@ PWM_CTRL_PRSC0
Definition: neorv32.h:781
@ PWM_CTRL_PRSC2
Definition: neorv32.h:783
@ PWM_CTRL_PRSC1
Definition: neorv32.h:782
@ PWM_CTRL_EN
Definition: neorv32.h:780
NEORV32_CSR_MISA_enum
Definition: neorv32.h:431
@ CSR_MISA_E
Definition: neorv32.h:436
@ CSR_MISA_X
Definition: neorv32.h:441
@ CSR_MISA_D
Definition: neorv32.h:435
@ CSR_MISA_M
Definition: neorv32.h:439
@ CSR_MISA_I
Definition: neorv32.h:438
@ CSR_MISA_C
Definition: neorv32.h:434
@ CSR_MISA_A
Definition: neorv32.h:432
@ CSR_MISA_F
Definition: neorv32.h:437
@ CSR_MISA_MXL_LO
Definition: neorv32.h:442
@ CSR_MISA_U
Definition: neorv32.h:440
@ CSR_MISA_B
Definition: neorv32.h:433
@ CSR_MISA_MXL_HI
Definition: neorv32.h:443
NEORV32_UART_PARITY_enum
Definition: neorv32.h:1046
@ PARITY_ODD
Definition: neorv32.h:1049
@ PARITY_NONE
Definition: neorv32.h:1047
@ PARITY_EVEN
Definition: neorv32.h:1048
Custom Functions Subsystem (CFS)) HW driver header file.
CPU Core Functions HW driver header file.
CPU Core custom functions unit HW driver header file.
General purpose input/output port unit (GPIO) HW driver header file.
General purpose timer (GPTMR) HW driver header file.
Helper functions and macros for custom "intrinsics" / instructions.
Machine System Timer (MTIME) HW driver header file.
Smart LED Interface (NEOLED) HW driver header file.
Pulse-Width Modulation Controller (PWM) HW driver header file.
NEORV32 Runtime Environment.
Serial peripheral interface controller (SPI) HW driver header file.
True Random Number Generator (TRNG) HW driver header file.
Two-Wire Interface Controller (TWI) HW driver header file.
Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file.
Watchdog Timer (WDT) HW driver header file.
Execute in place module (XIP) HW driver header file.
External Interrupt controller HW driver header file.
Definition: neorv32.h:923
uint32_t CTRL
Definition: neorv32.h:924
Definition: neorv32.h:750
Definition: neorv32.h:689
uint32_t SREG
Definition: neorv32.h:695
uint32_t DATA
Definition: neorv32.h:693
Definition: neorv32.h:1225
uint32_t OUTPUT_LO
Definition: neorv32.h:1228
const uint32_t INPUT_LO
Definition: neorv32.h:1226
uint32_t OUTPUT_HI
Definition: neorv32.h:1229
const uint32_t INPUT_HI
Definition: neorv32.h:1227
Definition: neorv32.h:894
uint32_t COUNT
Definition: neorv32.h:897
uint32_t CTRL
Definition: neorv32.h:895
uint32_t THRES
Definition: neorv32.h:896
const uint32_t reserved
Definition: neorv32.h:898
Definition: neorv32.h:966
uint32_t TIME_HI
Definition: neorv32.h:968
uint32_t TIMECMP_LO
Definition: neorv32.h:969
uint32_t TIME_LO
Definition: neorv32.h:967
uint32_t TIMECMP_HI
Definition: neorv32.h:970
Definition: neorv32.h:1245
uint32_t DATA
Definition: neorv32.h:1247
uint32_t CTRL
Definition: neorv32.h:1246
Definition: neorv32.h:767
uint32_t CTRL
Definition: neorv32.h:768
Definition: neorv32.h:1078
uint32_t CTRL
Definition: neorv32.h:1079
uint32_t DATA
Definition: neorv32.h:1080
Definition: neorv32.h:1302
const uint32_t reserved
Definition: neorv32.h:1304
const uint32_t DSPACE_BASE
Definition: neorv32.h:1308
const uint32_t DMEM_SIZE
Definition: neorv32.h:1310
const uint32_t IMEM_SIZE
Definition: neorv32.h:1309
const uint32_t SOC
Definition: neorv32.h:1305
const uint32_t ISPACE_BASE
Definition: neorv32.h:1307
const uint32_t CACHE
Definition: neorv32.h:1306
const uint32_t CLK
Definition: neorv32.h:1303
Definition: neorv32.h:1158
uint32_t CTRL
Definition: neorv32.h:1159
Definition: neorv32.h:1119
uint32_t CTRL
Definition: neorv32.h:1120
uint32_t DATA
Definition: neorv32.h:1121
Definition: neorv32.h:986
uint32_t DATA
Definition: neorv32.h:988
uint32_t CTRL
Definition: neorv32.h:987
Definition: neorv32.h:998
uint32_t CTRL
Definition: neorv32.h:999
uint32_t DATA
Definition: neorv32.h:1000
Definition: neorv32.h:1186
uint32_t CTRL
Definition: neorv32.h:1187
Definition: neorv32.h:850
uint32_t DATA_HI
Definition: neorv32.h:854
uint32_t CTRL
Definition: neorv32.h:851
const uint32_t reserved
Definition: neorv32.h:852
uint32_t DATA_LO
Definition: neorv32.h:853
Definition: neorv32.h:946
uint32_t SCR
Definition: neorv32.h:949
const uint32_t reserved
Definition: neorv32.h:950
uint32_t IPR
Definition: neorv32.h:948
uint32_t IER
Definition: neorv32.h:947