NEORV32 Software Framework Documentation
The NEORV32 RISC-V Processor
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neorv32.h
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1// ================================================================================ //
2// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
3// Copyright (c) NEORV32 contributors. //
4// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
5// Licensed under the BSD-3-Clause license, see LICENSE for details. //
6// SPDX-License-Identifier: BSD-3-Clause //
7// ================================================================================ //
8
13
14#ifndef neorv32_h
15#define neorv32_h
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21// Standard libraries
22#include <stdint.h>
23#include <inttypes.h>
24#include <unistd.h>
25#include <stdlib.h>
26
27
28/**********************************************************************/
33#define XIP_MEM_BASE_ADDRESS (0xE0000000U)
35#define IO_BASE_ADDRESS (0XFFE00000U)
37
38
39/**********************************************************************/
43#define NEORV32_BOOTROM_BASE (0xFFE00000U)
44//#define NEORV32_???_BASE (0xFFE10000U) /**< reserved */
45//#define NEORV32_???_BASE (0xFFE20000U) /**< reserved */
46//#define NEORV32_???_BASE (0xFFE30000U) /**< reserved */
47//#define NEORV32_???_BASE (0xFFE40000U) /**< reserved */
48//#define NEORV32_???_BASE (0xFFE50000U) /**< reserved */
49//#define NEORV32_???_BASE (0xFFE60000U) /**< reserved */
50//#define NEORV32_???_BASE (0xFFE70000U) /**< reserved */
51//#define NEORV32_???_BASE (0xFFE80000U) /**< reserved */
52//#define NEORV32_???_BASE (0xFFE90000U) /**< reserved */
53#define NEORV32_TWD_BASE (0xFFEA0000U)
54#define NEORV32_CFS_BASE (0xFFEB0000U)
55#define NEORV32_SLINK_BASE (0xFFEC0000U)
56#define NEORV32_DMA_BASE (0xFFED0000U)
57#define NEORV32_CRC_BASE (0xFFEE0000U)
58#define NEORV32_XIP_BASE (0xFFEF0000U)
59#define NEORV32_PWM_BASE (0xFFF00000U)
60#define NEORV32_GPTMR_BASE (0xFFF10000U)
61#define NEORV32_ONEWIRE_BASE (0xFFF20000U)
62//#define NEORV32_???_BASE (0xFFF30000U) /**< reserved */
63#define NEORV32_CLINT_BASE (0xFFF40000U)
64#define NEORV32_UART0_BASE (0xFFF50000U)
65#define NEORV32_UART1_BASE (0xFFF60000U)
66#define NEORV32_SDI_BASE (0xFFF70000U)
67#define NEORV32_SPI_BASE (0xFFF80000U)
68#define NEORV32_TWI_BASE (0xFFF90000U)
69#define NEORV32_TRNG_BASE (0xFFFA0000U)
70#define NEORV32_WDT_BASE (0xFFFB0000U)
71#define NEORV32_GPIO_BASE (0xFFFC0000U)
72#define NEORV32_NEOLED_BASE (0xFFFD0000U)
73#define NEORV32_SYSINFO_BASE (0xFFFE0000U)
74#define NEORV32_DM_BASE (0xFFFF0000U)
76
77
78/**********************************************************************/
84#define TWD_FIRQ_ENABLE CSR_MIE_FIRQ0E
85#define TWD_FIRQ_PENDING CSR_MIP_FIRQ0P
86#define TWD_RTE_ID RTE_TRAP_FIRQ_0
87#define TWD_TRAP_CODE TRAP_CODE_FIRQ_0
91#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E
92#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P
93#define CFS_RTE_ID RTE_TRAP_FIRQ_1
94#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1
98#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E
99#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P
100#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2
101#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2
102#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E
103#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P
104#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3
105#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_3
109#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E
110#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P
111#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4
112#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4
113#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E
114#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P
115#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5
116#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5
120#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E
121#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P
122#define SPI_RTE_ID RTE_TRAP_FIRQ_6
123#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6
127#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E
128#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P
129#define TWI_RTE_ID RTE_TRAP_FIRQ_7
130#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7
134#define GPIO_FIRQ_ENABLE CSR_MIE_FIRQ8E
135#define GPIO_FIRQ_PENDING CSR_MIP_FIRQ8P
136#define GPIO_RTE_ID RTE_TRAP_FIRQ_8
137#define GPIO_TRAP_CODE TRAP_CODE_FIRQ_8
141#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E
142#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P
143#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9
144#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9
148#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E
149#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P
150#define DMA_RTE_ID RTE_TRAP_FIRQ_10
151#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10
155#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E
156#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P
157#define SDI_RTE_ID RTE_TRAP_FIRQ_11
158#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11
162#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E
163#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P
164#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12
165#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12
169#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E
170#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P
171#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13
172#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13
176#define SLINK_RX_FIRQ_ENABLE CSR_MIE_FIRQ14E
177#define SLINK_RX_FIRQ_PENDING CSR_MIP_FIRQ14P
178#define SLINK_RX_RTE_ID RTE_TRAP_FIRQ_14
179#define SLINK_RX_TRAP_CODE TRAP_CODE_FIRQ_14
180#define SLINK_TX_FIRQ_ENABLE CSR_MIE_FIRQ15E
181#define SLINK_TX_FIRQ_PENDING CSR_MIP_FIRQ15P
182#define SLINK_TX_RTE_ID RTE_TRAP_FIRQ_15
183#define SLINK_TX_TRAP_CODE TRAP_CODE_FIRQ_15
186
187
188/**********************************************************************/
192extern char __heap_start[];
193extern char __heap_end[];
194extern char __crt0_max_heap[];
195// aliases
196#define neorv32_heap_begin_c ((uint32_t)&__heap_start[0])
197#define neorv32_heap_end_c ((uint32_t)&__heap_end[0])
198#define neorv32_heap_size_c ((uint32_t)&__crt0_max_heap[0])
200
201
202/**********************************************************************/
216
217
218
219/**********************************************************************/
224typedef union {
225 uint64_t uint64;
226 uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
227 uint16_t uint16[sizeof(uint64_t)/sizeof(uint16_t)];
228 uint8_t uint8[ sizeof(uint64_t)/sizeof(uint8_t)];
230
231typedef union {
232 uint32_t uint32[sizeof(uint32_t)/sizeof(uint32_t)];
233 uint16_t uint16[sizeof(uint32_t)/sizeof(uint16_t)];
234 uint8_t uint8[ sizeof(uint32_t)/sizeof(uint8_t)];
236
237typedef union {
238 uint16_t uint16[sizeof(uint16_t)/sizeof(uint16_t)];
239 uint8_t uint8[ sizeof(uint16_t)/sizeof(uint8_t)];
241
242
243
244// ----------------------------------------------------------------------------
245// Include all system header files
246// ----------------------------------------------------------------------------
247// intrinsics
248#include "neorv32_intrinsics.h"
249
250// helper functions
251#include "neorv32_aux.h"
252
253// CPU core
254#include "neorv32_cpu.h"
255#include "neorv32_cpu_csr.h"
256#include "neorv32_cpu_cfu.h"
257
258// NEORV32 runtime environment
259#include "neorv32_rte.h"
260#include "neorv32_smp.h"
261
262// IO/peripheral devices
263#include "neorv32_cfs.h"
264#include "neorv32_clint.h"
265#include "neorv32_crc.h"
266#include "neorv32_dma.h"
267#include "neorv32_gpio.h"
268#include "neorv32_gptmr.h"
269#include "neorv32_neoled.h"
270#include "neorv32_onewire.h"
271#include "neorv32_pwm.h"
272#include "neorv32_sdi.h"
273#include "neorv32_slink.h"
274#include "neorv32_spi.h"
275#include "neorv32_sysinfo.h"
276#include "neorv32_trng.h"
277#include "neorv32_twd.h"
278#include "neorv32_twi.h"
279#include "neorv32_uart.h"
280#include "neorv32_wdt.h"
281#include "neorv32_xip.h"
282
283
284#ifdef __cplusplus
285}
286#endif
287
288#endif // neorv32_h
char __heap_start[]
NEORV32_CLOCK_PRSC_enum
Definition neorv32.h:206
@ CLK_PRSC_4096
Definition neorv32.h:214
@ CLK_PRSC_1024
Definition neorv32.h:212
@ CLK_PRSC_64
Definition neorv32.h:210
@ CLK_PRSC_4
Definition neorv32.h:208
@ CLK_PRSC_128
Definition neorv32.h:211
@ CLK_PRSC_2048
Definition neorv32.h:213
@ CLK_PRSC_8
Definition neorv32.h:209
@ CLK_PRSC_2
Definition neorv32.h:207
char __crt0_max_heap[]
char __heap_end[]
General auxiliary functions header file.
Custom Functions Subsystem (CFS) HW driver header file.
Hardware Local Interruptor (CLINT) HW driver header file.
CPU Core Functions HW driver header file.
CPU Core custom functions unit HW driver header file.
Control and Status Registers (CSR) definitions.
Cyclic redundancy check unit (CRC) HW driver header file.
Direct Memory Access Controller (DMA) HW driver header file.
General purpose input/output port unit (GPIO) HW driver header file.
General purpose timer (GPTMR) HW driver header file.
Helper macros for custom "intrinsics" / instructions.
Smart LED Interface (NEOLED) HW driver header file.
1-Wire Interface Controller (ONEWIRE) HW driver header file.
Pulse-Width Modulation Controller (PWM) HW driver header file.
NEORV32 Runtime Environment.
Serial data interface controller (SPPI) HW driver header file.
Symmetric multiprocessing (SMP) library header file.
Serial peripheral interface controller (SPI) HW driver header file.
System Information Memory (SYSINFO) HW driver header file.
True Random Number Generator (TRNG) HW driver header file.
Two-Wire Device Controller (TWD) HW driver header file.
Two-Wire Interface Controller (TWI) HW driver header file.
Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file.
Watchdog Timer (WDT) HW driver header file.
Execute in place module (XIP) HW driver header file.
Definition neorv32.h:237
Definition neorv32.h:231
Definition neorv32.h:224