neorv32.h

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// ================================================================================ //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
// Copyright (c) NEORV32 contributors.                                              //
// Copyright (c) 2020 - 2026 Stephan Nolting. All rights reserved.                  //
// Licensed under the BSD-3-Clause license, see LICENSE for details.                //
// SPDX-License-Identifier: BSD-3-Clause                                            //
// ================================================================================ //
 
#ifndef NEORV32_H
#define NEORV32_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
// Standard libraries
#include <stdint.h>
#include <inttypes.h>
#include <stdlib.h>
 
// required for semihosting
#if defined(STDIO_SEMIHOSTING)
#include <stdio.h>
#include <string.h>
#include <fcntl.h>  // for open()
#include <unistd.h> // for close()
#endif
 
/**********************************************************************/
#define IO_BASE_ADDRESS       (0XFFE00000U)
#define NEORV32_BOOTROM_BASE  (0xFFE00000U) 
//#define NEORV32_???_BASE    (0xFFE10000U) /**< reserved */
//#define NEORV32_???_BASE    (0xFFE20000U) /**< reserved */
//#define NEORV32_???_BASE    (0xFFE30000U) /**< reserved */
//#define NEORV32_???_BASE    (0xFFE40000U) /**< reserved */
//#define NEORV32_???_BASE    (0xFFE50000U) /**< reserved */
//#define NEORV32_???_BASE    (0xFFE60000U) /**< reserved */
//#define NEORV32_???_BASE    (0xFFE70000U) /**< reserved */
//#define NEORV32_???_BASE    (0xFFE80000U) /**< reserved */
//#define NEORV32_???_BASE    (0xFFE90000U) /**< reserved */
#define NEORV32_TWD_BASE      (0xFFEA0000U) 
#define NEORV32_CFS_BASE      (0xFFEB0000U) 
#define NEORV32_SLINK_BASE    (0xFFEC0000U) 
#define NEORV32_DMA_BASE      (0xFFED0000U) 
//#define NEORV32_???_BASE    (0xFFEE0000U) /**< reserved */
#define NEORV32_SMC_BASE      (0xFFEF0000U) 
#define NEORV32_PWM_BASE      (0xFFF00000U) 
#define NEORV32_GPTMR_BASE    (0xFFF10000U) 
#define NEORV32_ONEWIRE_BASE  (0xFFF20000U) 
#define NEORV32_TRACEBUF_BASE (0xFFF30000U) 
#define NEORV32_CLINT_BASE    (0xFFF40000U) 
#define NEORV32_UART0_BASE    (0xFFF50000U) 
#define NEORV32_UART1_BASE    (0xFFF60000U) 
#define NEORV32_SDI_BASE      (0xFFF70000U) 
#define NEORV32_SPI_BASE      (0xFFF80000U) 
#define NEORV32_TWI_BASE      (0xFFF90000U) 
#define NEORV32_TRNG_BASE     (0xFFFA0000U) 
#define NEORV32_WDT_BASE      (0xFFFB0000U) 
#define NEORV32_GPIO_BASE     (0xFFFC0000U) 
#define NEORV32_NEOLED_BASE   (0xFFFD0000U) 
#define NEORV32_SYSINFO_BASE  (0xFFFE0000U) 
#define NEORV32_DM_BASE       (0xFFFF0000U) 
/**********************************************************************/
#define CFS_FIRQ_ENABLE        CSR_MIE_FIRQ1E    
#define CFS_FIRQ_PENDING       CSR_MIP_FIRQ1P    
#define CFS_TRAP_CODE          TRAP_CODE_FIRQ_1  
#define UART0_FIRQ_ENABLE      CSR_MIE_FIRQ2E    
#define UART0_FIRQ_PENDING     CSR_MIP_FIRQ2P    
#define UART0_TRAP_CODE        TRAP_CODE_FIRQ_2  
#define UART1_FIRQ_ENABLE      CSR_MIE_FIRQ3E    
#define UART1_FIRQ_PENDING     CSR_MIP_FIRQ3P    
#define UART1_TRAP_CODE        TRAP_CODE_FIRQ_3  
#define TWD_FIRQ_ENABLE        CSR_MIE_FIRQ4E    
#define TWD_FIRQ_PENDING       CSR_MIP_FIRQ4P    
#define TWD_TRAP_CODE          TRAP_CODE_FIRQ_4  
#define TRACEBUF_FIRQ_ENABLE   CSR_MIE_FIRQ5E    
#define TRACEBUF_FIRQ_PENDING  CSR_MIP_FIRQ5P    
#define TRACEBUF_TRAP_CODE     TRAP_CODE_FIRQ_5  
#define SPI_FIRQ_ENABLE        CSR_MIE_FIRQ6E    
#define SPI_FIRQ_PENDING       CSR_MIP_FIRQ6P    
#define SPI_TRAP_CODE          TRAP_CODE_FIRQ_6  
#define TWI_FIRQ_ENABLE        CSR_MIE_FIRQ7E    
#define TWI_FIRQ_PENDING       CSR_MIP_FIRQ7P    
#define TWI_TRAP_CODE          TRAP_CODE_FIRQ_7  
#define GPIO_FIRQ_ENABLE       CSR_MIE_FIRQ8E    
#define GPIO_FIRQ_PENDING      CSR_MIP_FIRQ8P    
#define GPIO_TRAP_CODE         TRAP_CODE_FIRQ_8  
#define NEOLED_FIRQ_ENABLE     CSR_MIE_FIRQ9E    
#define NEOLED_FIRQ_PENDING    CSR_MIP_FIRQ9P    
#define NEOLED_TRAP_CODE       TRAP_CODE_FIRQ_9  
#define DMA_FIRQ_ENABLE        CSR_MIE_FIRQ10E   
#define DMA_FIRQ_PENDING       CSR_MIP_FIRQ10P   
#define DMA_TRAP_CODE          TRAP_CODE_FIRQ_10 
#define SDI_FIRQ_ENABLE        CSR_MIE_FIRQ11E   
#define SDI_FIRQ_PENDING       CSR_MIP_FIRQ11P   
#define SDI_TRAP_CODE          TRAP_CODE_FIRQ_11 
#define GPTMR_FIRQ_ENABLE      CSR_MIE_FIRQ12E   
#define GPTMR_FIRQ_PENDING     CSR_MIP_FIRQ12P   
#define GPTMR_TRAP_CODE        TRAP_CODE_FIRQ_12 
#define ONEWIRE_FIRQ_ENABLE    CSR_MIE_FIRQ13E   
#define ONEWIRE_FIRQ_PENDING   CSR_MIP_FIRQ13P   
#define ONEWIRE_TRAP_CODE      TRAP_CODE_FIRQ_13 
#define SLINK_FIRQ_ENABLE      CSR_MIE_FIRQ14E   
#define SLINK_FIRQ_PENDING     CSR_MIP_FIRQ14P   
#define SLINK_TRAP_CODE        TRAP_CODE_FIRQ_14 
#define TRNG_FIRQ_ENABLE       CSR_MIE_FIRQ15E   
#define TRNG_FIRQ_PENDING      CSR_MIP_FIRQ15P   
#define TRNG_TRAP_CODE         TRAP_CODE_FIRQ_15 
/**********************************************************************/
extern char __heap_start[];    
extern char __heap_end[];      
extern char __crt0_max_heap[]; 
extern char __crt0_entry[];    
extern char __crt0_rom_base[]; 
extern char __crt0_rom_size[]; 
extern char __crt0_ram_base[]; 
extern char __crt0_ram_size[]; 
// aliases
#define NEORV32_HEAP_BEGIN ((uint32_t)&__heap_start[0])
#define NEORV32_HEAP_END   ((uint32_t)&__heap_end[0])
#define NEORV32_HEAP_SIZE  ((uint32_t)&__crt0_max_heap[0])
#define NEORV32_CRT0_ENTRY ((uint32_t)&__crt0_entry[0])
#define NEORV32_ROM_BASE   ((uint32_t)&__crt0_rom_base[0])
#define NEORV32_ROM_SIZE   ((uint32_t)&__crt0_rom_size[0])
#define NEORV32_RAM_BASE   ((uint32_t)&__crt0_ram_base[0])
#define NEORV32_RAM_SIZE   ((uint32_t)&__crt0_ram_size[0])
/**********************************************************************/
enum NEORV32_CLOCK_PRSC_enum {
  CLK_PRSC_2    = 0, 
  CLK_PRSC_4    = 1, 
  CLK_PRSC_8    = 2, 
  CLK_PRSC_64   = 3, 
  CLK_PRSC_128  = 4, 
  CLK_PRSC_1024 = 5, 
  CLK_PRSC_2048 = 6, 
  CLK_PRSC_4096 = 7  
};
/**********************************************************************/
typedef union {
  uint64_t uint64;
  uint32_t uint32[2];
  uint16_t uint16[4];
  uint8_t  uint8[8];
} subwords64_t;
 
typedef union {
  uint32_t uint32;
  uint16_t uint16[2];
  uint8_t  uint8[4];
} subwords32_t;
 
typedef union {
  uint16_t uint16;
  uint8_t  uint8[2];
} subwords16_t;
/**********************************************************************/
// generic
#define __MMREG_BSET(r, m) ((r) |=  (m))
#define __MMREG_BCLR(r, m) ((r) &= ~(m))
#define __MMREG_BINV(r, m) ((r) ^=  (m))
// 32-bit access
#if defined(__riscv_a) || defined(__riscv_zaamo) // use atomic RMW instructions
#define __MMREG32_BSET(r, m) (neorv32_cpu_amoor( (uint32_t)(&r),  (uint32_t)(m)))
#define __MMREG32_BCLR(r, m) (neorv32_cpu_amoand((uint32_t)(&r), ~(uint32_t)(m)))
#define __MMREG32_BINV(r, m) (neorv32_cpu_amoxor((uint32_t)(&r),  (uint32_t)(m)))
#else // use individual load + modify + write instructions
#define __MMREG32_BSET(r, m) __MMREG_BSET(r, (uint32_t)(m))
#define __MMREG32_BCLR(r, m) __MMREG_BCLR(r, (uint32_t)(m))
#define __MMREG32_BINV(r, m) __MMREG_BINV(r, (uint32_t)(m))
#endif
// 16-bit access
#define __MMREG16_BSET(r, m) __MMREG_BSET(r, (uint16_t)(m))
#define __MMREG16_BCLR(r, m) __MMREG_BCLR(r, (uint16_t)(m))
#define __MMREG16_BINV(r, m) __MMREG_BINV(r, (uint16_t)(m))
// 8-bit access
#define __MMREG8_BSET(r, m) __MMREG_BSET(r, (uint8_t)(m))
#define __MMREG8_BCLR(r, m) __MMREG_BCLR(r, (uint8_t)(m))
#define __MMREG8_BINV(r, m) __MMREG_BINV(r, (uint8_t)(m))
/**********************************************************************/
#include "neorv32_aux.h"
#include "neorv32_cfs.h"
#include "neorv32_clint.h"
#include "neorv32_cpu.h"
#include "neorv32_csr.h"
#include "neorv32_dma.h"
#include "neorv32_gpio.h"
#include "neorv32_gptmr.h"
#include "neorv32_intrinsics.h"
#include "neorv32_neoled.h"
#include "neorv32_onewire.h"
#include "neorv32_pwm.h"
#include "neorv32_rte.h"
#include "neorv32_semihosting.h"
#include "neorv32_sdi.h"
#include "neorv32_slink.h"
#include "neorv32_smc.h"
#include "neorv32_smp.h"
#include "neorv32_spi.h"
#include "neorv32_sysinfo.h"
#include "neorv32_tracebuf.h"
#include "neorv32_trng.h"
#include "neorv32_twd.h"
#include "neorv32_twi.h"
#include "neorv32_uart.h"
#include "neorv32_wdt.h"
#ifdef __cplusplus
}
#endif
 
#endif // NEORV32_H