30#define IO_BASE_ADDRESS (0XFFE00000U)
31#define NEORV32_BOOTROM_BASE (0xFFE00000U)
41#define NEORV32_TWD_BASE (0xFFEA0000U)
42#define NEORV32_CFS_BASE (0xFFEB0000U)
43#define NEORV32_SLINK_BASE (0xFFEC0000U)
44#define NEORV32_DMA_BASE (0xFFED0000U)
47#define NEORV32_PWM_BASE (0xFFF00000U)
48#define NEORV32_GPTMR_BASE (0xFFF10000U)
49#define NEORV32_ONEWIRE_BASE (0xFFF20000U)
51#define NEORV32_CLINT_BASE (0xFFF40000U)
52#define NEORV32_UART0_BASE (0xFFF50000U)
53#define NEORV32_UART1_BASE (0xFFF60000U)
54#define NEORV32_SDI_BASE (0xFFF70000U)
55#define NEORV32_SPI_BASE (0xFFF80000U)
56#define NEORV32_TWI_BASE (0xFFF90000U)
57#define NEORV32_TRNG_BASE (0xFFFA0000U)
58#define NEORV32_WDT_BASE (0xFFFB0000U)
59#define NEORV32_GPIO_BASE (0xFFFC0000U)
60#define NEORV32_NEOLED_BASE (0xFFFD0000U)
61#define NEORV32_SYSINFO_BASE (0xFFFE0000U)
62#define NEORV32_DM_BASE (0xFFFF0000U)
72#define TWD_FIRQ_ENABLE CSR_MIE_FIRQ0E
73#define TWD_FIRQ_PENDING CSR_MIP_FIRQ0P
74#define TWD_RTE_ID RTE_TRAP_FIRQ_0
75#define TWD_TRAP_CODE TRAP_CODE_FIRQ_0
79#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E
80#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P
81#define CFS_RTE_ID RTE_TRAP_FIRQ_1
82#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1
86#define UART0_FIRQ_ENABLE CSR_MIE_FIRQ2E
87#define UART0_FIRQ_PENDING CSR_MIP_FIRQ2P
88#define UART0_RTE_ID RTE_TRAP_FIRQ_2
89#define UART0_TRAP_CODE TRAP_CODE_FIRQ_2
93#define UART1_FIRQ_ENABLE CSR_MIE_FIRQ3E
94#define UART1_FIRQ_PENDING CSR_MIP_FIRQ3P
95#define UART1_RTE_ID RTE_TRAP_FIRQ_3
96#define UART1_TRAP_CODE TRAP_CODE_FIRQ_3
100#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E
101#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P
102#define SPI_RTE_ID RTE_TRAP_FIRQ_6
103#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6
107#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E
108#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P
109#define TWI_RTE_ID RTE_TRAP_FIRQ_7
110#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7
114#define GPIO_FIRQ_ENABLE CSR_MIE_FIRQ8E
115#define GPIO_FIRQ_PENDING CSR_MIP_FIRQ8P
116#define GPIO_RTE_ID RTE_TRAP_FIRQ_8
117#define GPIO_TRAP_CODE TRAP_CODE_FIRQ_8
121#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E
122#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P
123#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9
124#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9
128#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E
129#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P
130#define DMA_RTE_ID RTE_TRAP_FIRQ_10
131#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10
135#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E
136#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P
137#define SDI_RTE_ID RTE_TRAP_FIRQ_11
138#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11
142#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E
143#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P
144#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12
145#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12
149#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E
150#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P
151#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13
152#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13
156#define SLINK_FIRQ_ENABLE CSR_MIE_FIRQ14E
157#define SLINK_FIRQ_PENDING CSR_MIP_FIRQ14P
158#define SLINK_RTE_ID RTE_TRAP_FIRQ_14
159#define SLINK_TRAP_CODE TRAP_CODE_FIRQ_14
163#define TRNG_FIRQ_ENABLE CSR_MIE_FIRQ15E
164#define TRNG_FIRQ_PENDING CSR_MIP_FIRQ15P
165#define TRNG_RTE_ID RTE_TRAP_FIRQ_15
166#define TRNG_TRAP_CODE TRAP_CODE_FIRQ_15
180#define NEORV32_HEAP_BEGIN ((uint32_t)&__heap_start[0])
181#define NEORV32_HEAP_END ((uint32_t)&__heap_end[0])
182#define NEORV32_HEAP_SIZE ((uint32_t)&__crt0_max_heap[0])
183#define NEORV32_CRT0_ENTRY ((uint32_t)&__crt0_entry[0])
211 uint32_t uint32[
sizeof(uint64_t)/
sizeof(uint32_t)];
212 uint16_t uint16[
sizeof(uint64_t)/
sizeof(uint16_t)];
213 uint8_t uint8[
sizeof(uint64_t)/
sizeof(uint8_t)];
218 uint16_t uint16[
sizeof(uint32_t)/
sizeof(uint16_t)];
219 uint8_t uint8[
sizeof(uint32_t)/
sizeof(uint8_t)];
224 uint8_t uint8[
sizeof(uint16_t)/
sizeof(uint8_t)];
NEORV32_CLOCK_PRSC_enum
Definition neorv32.h:191
@ CLK_PRSC_4096
Definition neorv32.h:199
@ CLK_PRSC_1024
Definition neorv32.h:197
@ CLK_PRSC_64
Definition neorv32.h:195
@ CLK_PRSC_4
Definition neorv32.h:193
@ CLK_PRSC_128
Definition neorv32.h:196
@ CLK_PRSC_2048
Definition neorv32.h:198
@ CLK_PRSC_8
Definition neorv32.h:194
@ CLK_PRSC_2
Definition neorv32.h:192
General auxiliary functions header file.
Custom Functions Subsystem (CFS) HW driver header file.
Hardware Local Interruptor (CLINT) HW driver header file.
CPU Core Functions HW driver header file.
CPU Core custom functions unit HW driver header file.
Control and Status Registers (CSR) definitions.
Direct Memory Access Controller (DMA) HW driver header file.
General purpose input/output port unit (GPIO) HW driver header file.
General purpose timer (GPTMR) HW driver header file.
Helper macros for custom "intrinsics" / instructions.
Smart LED Interface (NEOLED) HW driver header file.
1-Wire Interface Controller (ONEWIRE) HW driver header file.
Pulse-Width Modulation Controller (PWM) HW driver header file.
NEORV32 Runtime Environment.
Serial data interface controller (SPPI) HW driver header file.
RISC-V semihosting header file.
Stream Link Interface HW driver header file.
Symmetric multiprocessing (SMP) library header file.
Serial peripheral interface controller (SPI) HW driver header file.
System Information Memory (SYSINFO) HW driver header file.
True Random Number Generator (TRNG) HW driver header file.
Two-Wire Device Controller (TWD) HW driver header file.
Two-Wire Interface Controller (TWI) HW driver header file.
Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file.
Watchdog Timer (WDT) HW driver header file.