NEORV32 - Software Framework Documentation
Loading...
Searching...
No Matches
neorv32.h
Go to the documentation of this file.
1// #################################################################################################
2// # << NEORV32: neorv32.h - Main Core Library File >> #
3// # ********************************************************************************************* #
4// # BSD 3-Clause License #
5// # #
6// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
7// # #
8// # Redistribution and use in source and binary forms, with or without modification, are #
9// # permitted provided that the following conditions are met: #
10// # #
11// # 1. Redistributions of source code must retain the above copyright notice, this list of #
12// # conditions and the following disclaimer. #
13// # #
14// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
15// # conditions and the following disclaimer in the documentation and/or other materials #
16// # provided with the distribution. #
17// # #
18// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
19// # endorse or promote products derived from this software without specific prior written #
20// # permission. #
21// # #
22// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
23// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
24// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
25// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
26// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
28// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
29// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
30// # OF THE POSSIBILITY OF SUCH DAMAGE. #
31// # ********************************************************************************************* #
32// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
33// #################################################################################################
34
35
36/**********************************************************************/
43#ifndef neorv32_h
44#define neorv32_h
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50// Standard libraries
51#include <stdint.h>
52#include <inttypes.h>
53#include <limits.h>
54#include <unistd.h>
55#include <stdlib.h>
56
57
58/**********************************************************************/
71
72
73/**********************************************************************/
79#define WDT_FIRQ_ENABLE CSR_MIE_FIRQ0E
80#define WDT_FIRQ_PENDING CSR_MIP_FIRQ0P
81#define WDT_RTE_ID RTE_TRAP_FIRQ_0
82#define WDT_TRAP_CODE TRAP_CODE_FIRQ_0
86#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E
87#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P
88#define CFS_RTE_ID RTE_TRAP_FIRQ_1
89#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1
93#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E
94#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P
95#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2
96#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2
97#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E
98#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P
99#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3
100#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_3
104#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E
105#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P
106#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4
107#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4
108#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E
109#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P
110#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5
111#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5
115#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E
116#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P
117#define SPI_RTE_ID RTE_TRAP_FIRQ_6
118#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6
122#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E
123#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P
124#define TWI_RTE_ID RTE_TRAP_FIRQ_7
125#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7
129#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E
130#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P
131#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8
132#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8
136#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E
137#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P
138#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9
139#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9
143#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E
144#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P
145#define DMA_RTE_ID RTE_TRAP_FIRQ_10
146#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10
150#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E
151#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P
152#define SDI_RTE_ID RTE_TRAP_FIRQ_11
153#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11
157#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E
158#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P
159#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12
160#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12
164#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E
165#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P
166#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13
167#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13
171#define SLINK_FIRQ_ENABLE CSR_MIE_FIRQ14E
172#define SLINK_FIRQ_PENDING CSR_MIP_FIRQ14P
173#define SLINK_RTE_ID RTE_TRAP_FIRQ_14
174#define SLINK_TRAP_CODE TRAP_CODE_FIRQ_14
178#define TRNG_FIRQ_ENABLE CSR_MIE_FIRQ15E
179#define TRNG_FIRQ_PENDING CSR_MIP_FIRQ15P
180#define TRNG_RTE_ID RTE_TRAP_FIRQ_15
181#define TRNG_TRAP_CODE TRAP_CODE_FIRQ_15
186/**********************************************************************/
191#define XIP_MEM_BASE_ADDRESS (0xE0000000U)
193#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U)
195#define IO_BASE_ADDRESS (0xFFFFE000U)
199/**********************************************************************/
203#define NEORV32_CFS_BASE (0xFFFFEB00U)
204#define NEORV32_SLINK_BASE (0xFFFFEC00U)
205#define NEORV32_DMA_BASE (0xFFFFED00U)
206#define NEORV32_CRC_BASE (0xFFFFEE00U)
207#define NEORV32_XIP_BASE (0xFFFFEF00U)
208#define NEORV32_PWM_BASE (0xFFFFF000U)
209#define NEORV32_GPTMR_BASE (0xFFFFF100U)
210#define NEORV32_ONEWIRE_BASE (0xFFFFF200U)
211#define NEORV32_XIRQ_BASE (0xFFFFF300U)
212#define NEORV32_MTIME_BASE (0xFFFFF400U)
213#define NEORV32_UART0_BASE (0xFFFFF500U)
214#define NEORV32_UART1_BASE (0xFFFFF600U)
215#define NEORV32_SDI_BASE (0xFFFFF700U)
216#define NEORV32_SPI_BASE (0xFFFFF800U)
217#define NEORV32_TWI_BASE (0xFFFFF900U)
218#define NEORV32_TRNG_BASE (0xFFFFFA00U)
219#define NEORV32_WDT_BASE (0xFFFFFB00U)
220#define NEORV32_GPIO_BASE (0xFFFFFC00U)
221#define NEORV32_NEOLED_BASE (0xFFFFFD00U)
222#define NEORV32_SYSINFO_BASE (0xFFFFFE00U)
223#define NEORV32_DM_BASE (0xFFFFFF00U)
227// ----------------------------------------------------------------------------
228// Include all system header files
229// ----------------------------------------------------------------------------
230// intrinsics
231#include "neorv32_intrinsics.h"
232
233// cpu core
234#include "neorv32_cpu.h"
235#include "neorv32_cpu_amo.h"
236#include "neorv32_cpu_csr.h"
237#include "neorv32_cpu_cfu.h"
238
239// NEORV32 runtime environment
240#include "neorv32_rte.h"
241
242// IO/peripheral devices
243#include "neorv32_cfs.h"
244#include "neorv32_crc.h"
245#include "neorv32_dm.h"
246#include "neorv32_dma.h"
247#include "neorv32_gpio.h"
248#include "neorv32_gptmr.h"
249#include "neorv32_mtime.h"
250#include "neorv32_neoled.h"
251#include "neorv32_onewire.h"
252#include "neorv32_pwm.h"
253#include "neorv32_sdi.h"
254#include "neorv32_slink.h"
255#include "neorv32_spi.h"
256#include "neorv32_sysinfo.h"
257#include "neorv32_trng.h"
258#include "neorv32_twi.h"
259#include "neorv32_uart.h"
260#include "neorv32_wdt.h"
261#include "neorv32_xip.h"
262#include "neorv32_xirq.h"
263
264// backwards compatibility layer
265#include "legacy.h"
266
267#ifdef __cplusplus
268}
269#endif
270
271#endif // neorv32_h
Wrappers and functions for backwards compatibility.
NEORV32_CLOCK_PRSC_enum
Definition neorv32.h:61
@ CLK_PRSC_4096
Definition neorv32.h:69
@ CLK_PRSC_1024
Definition neorv32.h:67
@ CLK_PRSC_64
Definition neorv32.h:65
@ CLK_PRSC_4
Definition neorv32.h:63
@ CLK_PRSC_128
Definition neorv32.h:66
@ CLK_PRSC_2048
Definition neorv32.h:68
@ CLK_PRSC_8
Definition neorv32.h:64
@ CLK_PRSC_2
Definition neorv32.h:62
Custom Functions Subsystem (CFS) HW driver header file.
CPU Core Functions HW driver header file.
Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - header file.
CPU Core custom functions unit HW driver header file.
Control and Status Registers (CSR) definitions.
Cyclic redundancy check unit (CRC) HW driver header file.
On-Chip Debugger (CANNOT be accessed by application software!)
Direct Memory Access Controller (DMA) HW driver header file.
General purpose input/output port unit (GPIO) HW driver header file.
General purpose timer (GPTMR) HW driver header file.
Helper functions and macros for custom "intrinsics" / instructions.
Machine System Timer (MTIME) HW driver header file.
Smart LED Interface (NEOLED) HW driver header file.
1-Wire Interface Controller (ONEWIRE) HW driver header file.
Pulse-Width Modulation Controller (PWM) HW driver header file.
NEORV32 Runtime Environment.
Serial data interface controller (SPPI) HW driver header file.
Serial peripheral interface controller (SPI) HW driver header file.
True Random Number Generator (TRNG) HW driver header file.
Two-Wire Interface Controller (TWI) HW driver header file.
Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file.
Watchdog Timer (WDT) HW driver header file.
Execute in place module (XIP) HW driver header file.
External Interrupt controller HW driver header file.