77#define NEORV32_ARCHID 19
86#define WDT_FIRQ_ENABLE CSR_MIE_FIRQ0E
87#define WDT_FIRQ_PENDING CSR_MIP_FIRQ0P
88#define WDT_RTE_ID RTE_TRAP_FIRQ_0
89#define WDT_TRAP_CODE TRAP_CODE_FIRQ_0
93#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E
94#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P
95#define CFS_RTE_ID RTE_TRAP_FIRQ_1
96#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1
100#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E
101#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P
102#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2
103#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2
104#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E
105#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P
106#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3
107#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_3
111#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E
112#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P
113#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4
114#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4
115#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E
116#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P
117#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5
118#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5
122#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E
123#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P
124#define SPI_RTE_ID RTE_TRAP_FIRQ_6
125#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6
129#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E
130#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P
131#define TWI_RTE_ID RTE_TRAP_FIRQ_7
132#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7
136#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E
137#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P
138#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8
139#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8
143#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E
144#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P
145#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9
146#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9
150#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E
151#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P
152#define SDI_RTE_ID RTE_TRAP_FIRQ_11
153#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11
157#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E
158#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P
159#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12
160#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12
164#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E
165#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P
166#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13
167#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13
177#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000U)
179#define OCD_BASE_ADDRESS (0XFFFFF800U)
181#define IO_BASE_ADDRESS (0xFFFFFE00U)
189#define NEORV32_SYSINFO_BASE (0xFFFFFFE0U)
190#define NEORV32_NEOLED_BASE (0xFFFFFFD8U)
191#define NEORV32_UART1_BASE (0xFFFFFFD0U)
192#define NEORV32_GPIO_BASE (0xFFFFFFC0U)
193#define NEORV32_WDT_BASE (0xFFFFFFBCU)
194#define NEORV32_TRNG_BASE (0xFFFFFFB8U)
195#define NEORV32_TWI_BASE (0xFFFFFFB0U)
196#define NEORV32_SPI_BASE (0xFFFFFFA8U)
197#define NEORV32_UART0_BASE (0xFFFFFFA0U)
198#define NEORV32_MTIME_BASE (0xFFFFFF90U)
199#define NEORV32_XIRQ_BASE (0xFFFFFF80U)
200#define NEORV32_BUSKEEPER_BASE (0xFFFFFF78U)
201#define NEORV32_ONEWIRE_BASE (0xFFFFFF70U)
202#define NEORV32_GPTMR_BASE (0xFFFFFF60U)
203#define NEORV32_PWM_BASE (0xFFFFFF50U)
204#define NEORV32_XIP_BASE (0xFFFFFF40U)
205#define NEORV32_SDI_BASE (0xFFFFFF00U)
206#define NEORV32_CFS_BASE (0xFFFFFE00U)
207#define NEORV32_DM_BASE (0xFFFFF800U)
237#include "neorv32_sysinfo.h"
Wrappers and functions for backwards compatibility.
NEORV32_CLOCK_PRSC_enum
Definition: neorv32.h:61
@ CLK_PRSC_4096
Definition: neorv32.h:69
@ CLK_PRSC_1024
Definition: neorv32.h:67
@ CLK_PRSC_64
Definition: neorv32.h:65
@ CLK_PRSC_4
Definition: neorv32.h:63
@ CLK_PRSC_128
Definition: neorv32.h:66
@ CLK_PRSC_2048
Definition: neorv32.h:68
@ CLK_PRSC_8
Definition: neorv32.h:64
@ CLK_PRSC_2
Definition: neorv32.h:62
Bus Monitor (BUSKEEPER) HW driver header file.
Custom Functions Subsystem (CFS) HW driver header file.
CPU Core Functions HW driver header file.
CPU Core custom functions unit HW driver header file.
Control and Status Registers (CSR) definitions.
On-Chip Debugger (should NOT be used by application software at all!)
General purpose input/output port unit (GPIO) HW driver header file.
General purpose timer (GPTMR) HW driver header file.
Helper functions and macros for custom "intrinsics" / instructions.
Machine System Timer (MTIME) HW driver header file.
Smart LED Interface (NEOLED) HW driver header file.
1-Wire Interface Controller (ONEWIRE) HW driver header file.
Pulse-Width Modulation Controller (PWM) HW driver header file.
NEORV32 Runtime Environment.
Serial data interface controller (SPPI) HW driver header file.
Serial peripheral interface controller (SPI) HW driver header file.
True Random Number Generator (TRNG) HW driver header file.
Two-Wire Interface Controller (TWI) HW driver header file.
Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file.
Watchdog Timer (WDT) HW driver header file.
Execute in place module (XIP) HW driver header file.
External Interrupt controller HW driver header file.