NEORV32 Software Framework Documentation
The NEORV32 RISC-V Processor
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neorv32.h
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1// ================================================================================ //
2// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
3// Copyright (c) NEORV32 contributors. //
4// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
5// Licensed under the BSD-3-Clause license, see LICENSE for details. //
6// SPDX-License-Identifier: BSD-3-Clause //
7// ================================================================================ //
8
13
14#ifndef NEORV32_H
15#define NEORV32_H
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21// Standard libraries
22#include <stdint.h>
23#include <inttypes.h>
24#include <stdlib.h>
25
26// required for semihosting
27#if defined(STDIO_SEMIHOSTING)
28#include <stdio.h>
29#include <string.h>
30#include <fcntl.h> // for open
31#include <unistd.h> // for close
32#endif
33
34/**********************************************************************/
38#define IO_BASE_ADDRESS (0XFFE00000U)
39#define NEORV32_BOOTROM_BASE (0xFFE00000U)
40//#define NEORV32_???_BASE (0xFFE10000U) /**< reserved */
41//#define NEORV32_???_BASE (0xFFE20000U) /**< reserved */
42//#define NEORV32_???_BASE (0xFFE30000U) /**< reserved */
43//#define NEORV32_???_BASE (0xFFE40000U) /**< reserved */
44//#define NEORV32_???_BASE (0xFFE50000U) /**< reserved */
45//#define NEORV32_???_BASE (0xFFE60000U) /**< reserved */
46//#define NEORV32_???_BASE (0xFFE70000U) /**< reserved */
47//#define NEORV32_???_BASE (0xFFE80000U) /**< reserved */
48//#define NEORV32_???_BASE (0xFFE90000U) /**< reserved */
49#define NEORV32_TWD_BASE (0xFFEA0000U)
50#define NEORV32_CFS_BASE (0xFFEB0000U)
51#define NEORV32_SLINK_BASE (0xFFEC0000U)
52#define NEORV32_DMA_BASE (0xFFED0000U)
53//#define NEORV32_???_BASE (0xFFEE0000U) /**< reserved */
54//#define NEORV32_???_BASE (0xFFEF0000U) /**< reserved */
55#define NEORV32_PWM_BASE (0xFFF00000U)
56#define NEORV32_GPTMR_BASE (0xFFF10000U)
57#define NEORV32_ONEWIRE_BASE (0xFFF20000U)
58#define NEORV32_TRACER_BASE (0xFFF30000U)
59#define NEORV32_CLINT_BASE (0xFFF40000U)
60#define NEORV32_UART0_BASE (0xFFF50000U)
61#define NEORV32_UART1_BASE (0xFFF60000U)
62#define NEORV32_SDI_BASE (0xFFF70000U)
63#define NEORV32_SPI_BASE (0xFFF80000U)
64#define NEORV32_TWI_BASE (0xFFF90000U)
65#define NEORV32_TRNG_BASE (0xFFFA0000U)
66#define NEORV32_WDT_BASE (0xFFFB0000U)
67#define NEORV32_GPIO_BASE (0xFFFC0000U)
68#define NEORV32_NEOLED_BASE (0xFFFD0000U)
69#define NEORV32_SYSINFO_BASE (0xFFFE0000U)
70#define NEORV32_DM_BASE (0xFFFF0000U)
72
73
74/**********************************************************************/
80#define TWD_FIRQ_ENABLE CSR_MIE_FIRQ0E
81#define TWD_FIRQ_PENDING CSR_MIP_FIRQ0P
82#define TWD_TRAP_CODE TRAP_CODE_FIRQ_0
86#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E
87#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P
88#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1
92#define UART0_FIRQ_ENABLE CSR_MIE_FIRQ2E
93#define UART0_FIRQ_PENDING CSR_MIP_FIRQ2P
94#define UART0_TRAP_CODE TRAP_CODE_FIRQ_2
98#define UART1_FIRQ_ENABLE CSR_MIE_FIRQ3E
99#define UART1_FIRQ_PENDING CSR_MIP_FIRQ3P
100#define UART1_TRAP_CODE TRAP_CODE_FIRQ_3
104#define TRACER_FIRQ_ENABLE CSR_MIE_FIRQ5E
105#define TRACER_FIRQ_PENDING CSR_MIP_FIRQ5P
106#define TRACER_TRAP_CODE TRAP_CODE_FIRQ_5
110#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E
111#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P
112#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6
116#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E
117#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P
118#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7
122#define GPIO_FIRQ_ENABLE CSR_MIE_FIRQ8E
123#define GPIO_FIRQ_PENDING CSR_MIP_FIRQ8P
124#define GPIO_TRAP_CODE TRAP_CODE_FIRQ_8
128#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E
129#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P
130#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9
134#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E
135#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P
136#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10
140#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E
141#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P
142#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11
146#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E
147#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P
148#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12
152#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E
153#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P
154#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13
158#define SLINK_FIRQ_ENABLE CSR_MIE_FIRQ14E
159#define SLINK_FIRQ_PENDING CSR_MIP_FIRQ14P
160#define SLINK_TRAP_CODE TRAP_CODE_FIRQ_14
164#define TRNG_FIRQ_ENABLE CSR_MIE_FIRQ15E
165#define TRNG_FIRQ_PENDING CSR_MIP_FIRQ15P
166#define TRNG_TRAP_CODE TRAP_CODE_FIRQ_15
169
170
171/**********************************************************************/
175extern char __heap_start[];
176extern char __heap_end[];
177extern char __crt0_max_heap[];
178extern char __crt0_entry[];
179// aliases
180#define NEORV32_HEAP_BEGIN ((uint32_t)&__heap_start[0])
181#define NEORV32_HEAP_END ((uint32_t)&__heap_end[0])
182#define NEORV32_HEAP_SIZE ((uint32_t)&__crt0_max_heap[0])
183#define NEORV32_CRT0_ENTRY ((uint32_t)&__crt0_entry[0])
185
186
187/**********************************************************************/
201
202
203
204/**********************************************************************/
209typedef union {
210 uint64_t uint64;
211 uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
212 uint16_t uint16[sizeof(uint64_t)/sizeof(uint16_t)];
213 uint8_t uint8[sizeof(uint64_t)/sizeof(uint8_t)];
215
216typedef union {
217 uint32_t uint32;
218 uint16_t uint16[sizeof(uint32_t)/sizeof(uint16_t)];
219 uint8_t uint8[sizeof(uint32_t)/sizeof(uint8_t)];
221
222typedef union {
223 uint16_t uint16;
224 uint8_t uint8[sizeof(uint16_t)/sizeof(uint8_t)];
226
227
228
229// ----------------------------------------------------------------------------
230// Include all processor header files
231// ----------------------------------------------------------------------------
232// intrinsics
233#include "neorv32_intrinsics.h"
234
235// helper functions
236#include "neorv32_aux.h"
237
238// CPU core
239#include "neorv32_cpu.h"
240#include "neorv32_cpu_csr.h"
241#include "neorv32_cpu_cfu.h"
242
243// NEORV32 runtime environment
244#include "neorv32_rte.h"
245#include "neorv32_smp.h"
246#include "neorv32_semihosting.h"
247
248// IO/peripheral devices
249#include "neorv32_cfs.h"
250#include "neorv32_clint.h"
251#include "neorv32_dma.h"
252#include "neorv32_gpio.h"
253#include "neorv32_gptmr.h"
254#include "neorv32_neoled.h"
255#include "neorv32_onewire.h"
256#include "neorv32_pwm.h"
257#include "neorv32_sdi.h"
258#include "neorv32_slink.h"
259#include "neorv32_spi.h"
260#include "neorv32_sysinfo.h"
261#include "neorv32_tracer.h"
262#include "neorv32_trng.h"
263#include "neorv32_twd.h"
264#include "neorv32_twi.h"
265#include "neorv32_uart.h"
266#include "neorv32_wdt.h"
267
268// Legacy wrappers
269#include "neorv32_legacy.h"
270
271#ifdef __cplusplus
272}
273#endif
274
275#endif // NEORV32_H
char __crt0_entry[]
char __heap_start[]
NEORV32_CLOCK_PRSC_enum
Definition neorv32.h:191
@ CLK_PRSC_4096
Definition neorv32.h:199
@ CLK_PRSC_1024
Definition neorv32.h:197
@ CLK_PRSC_64
Definition neorv32.h:195
@ CLK_PRSC_4
Definition neorv32.h:193
@ CLK_PRSC_128
Definition neorv32.h:196
@ CLK_PRSC_2048
Definition neorv32.h:198
@ CLK_PRSC_8
Definition neorv32.h:194
@ CLK_PRSC_2
Definition neorv32.h:192
char __crt0_max_heap[]
char __heap_end[]
General auxiliary functions header file.
Custom Functions Subsystem (CFS) HW driver header file.
Hardware Local Interruptor (CLINT) HW driver header file.
CPU Core Functions HW driver header file.
CPU Core custom functions unit HW driver header file.
Control and Status Registers (CSR) definitions.
Direct Memory Access Controller (DMA) HW driver header file.
General purpose input/output port unit (GPIO) HW driver header file.
General purpose timer (GPTMR) HW driver header file.
Helper macros for custom "intrinsics" / instructions.
Legacy backwards compatibility layer.
Smart LED Interface (NEOLED) HW driver header file.
1-Wire Interface Controller (ONEWIRE) HW driver header file.
Pulse-Width Modulation Controller (PWM) HW driver header file.
NEORV32 Runtime Environment.
Serial data interface controller (SPPI) HW driver header file.
RISC-V semihosting header file.
Symmetric multiprocessing (SMP) library header file.
Serial peripheral interface controller (SPI) HW driver header file.
System Information Memory (SYSINFO) HW driver header file.
Execution trace buffer (TRACER) HW driver header file.
True Random Number Generator (TRNG) HW driver header file.
Two-Wire Device Controller (TWD) HW driver header file.
Two-Wire Interface Controller (TWI) HW driver header file.
Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file.
Watchdog Timer (WDT) HW driver header file.
Definition neorv32.h:222
Definition neorv32.h:216
Definition neorv32.h:209