neorv32.h

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// #################################################################################################
// # << NEORV32: neorv32.h - Main Core Library File >>                                             #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
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// #    conditions and the following disclaimer.                                                   #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    permission.                                                                                #
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// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************/
#ifndef neorv32_h
#define neorv32_h
 
#ifdef __cplusplus
extern "C" {
#endif
 
 
// Standard libraries
#include <stdint.h>
#include <inttypes.h>
#include <limits.h>
#include <unistd.h>
#include <stdlib.h>
 
 
/**********************************************************************/
enum NEORV32_CSR_enum {
  /* hardware-only CSR, NEORV32-specific, not accessible by software */
//CSR_ZERO           = 0x000, /**< 0x000 - zero (-/-): Always zero */
 
  /* floating-point unit control and status */
  CSR_FFLAGS         = 0x001, 
  CSR_FRM            = 0x002, 
  CSR_FCSR           = 0x003, 
  /* machine control and status */
  CSR_MSTATUS        = 0x300, 
  CSR_MISA           = 0x301, 
  CSR_MIE            = 0x304, 
  CSR_MTVEC          = 0x305, 
  CSR_MCOUNTEREN     = 0x306, 
  CSR_MENVCFG        = 0x30a, 
  CSR_MSTATUSH       = 0x310, 
  CSR_MENVCFGH       = 0x31a, 
  CSR_MCOUNTINHIBIT  = 0x320, 
  /* hardware performance monitors - event configuration */
  CSR_MHPMEVENT3     = 0x323, 
  CSR_MHPMEVENT4     = 0x324, 
  CSR_MHPMEVENT5     = 0x325, 
  CSR_MHPMEVENT6     = 0x326, 
  CSR_MHPMEVENT7     = 0x327, 
  CSR_MHPMEVENT8     = 0x328, 
  CSR_MHPMEVENT9     = 0x329, 
  CSR_MHPMEVENT10    = 0x32a, 
  CSR_MHPMEVENT11    = 0x32b, 
  CSR_MHPMEVENT12    = 0x32c, 
  CSR_MHPMEVENT13    = 0x32d, 
  CSR_MHPMEVENT14    = 0x32e, 
  CSR_MHPMEVENT15    = 0x32f, 
  CSR_MHPMEVENT16    = 0x330, 
  CSR_MHPMEVENT17    = 0x331, 
  CSR_MHPMEVENT18    = 0x332, 
  CSR_MHPMEVENT19    = 0x333, 
  CSR_MHPMEVENT20    = 0x334, 
  CSR_MHPMEVENT21    = 0x335, 
  CSR_MHPMEVENT22    = 0x336, 
  CSR_MHPMEVENT23    = 0x337, 
  CSR_MHPMEVENT24    = 0x338, 
  CSR_MHPMEVENT25    = 0x339, 
  CSR_MHPMEVENT26    = 0x33a, 
  CSR_MHPMEVENT27    = 0x33b, 
  CSR_MHPMEVENT28    = 0x33c, 
  CSR_MHPMEVENT29    = 0x33d, 
  CSR_MHPMEVENT30    = 0x33e, 
  CSR_MHPMEVENT31    = 0x33f, 
  /* machine trap control */
  CSR_MSCRATCH       = 0x340, 
  CSR_MEPC           = 0x341, 
  CSR_MCAUSE         = 0x342, 
  CSR_MTVAL          = 0x343, 
  CSR_MIP            = 0x344, 
  /* physical memory protection */
  CSR_PMPCFG0        = 0x3a0, 
  CSR_PMPCFG1        = 0x3a1, 
  CSR_PMPCFG2        = 0x3a2, 
  CSR_PMPCFG3        = 0x3a3, 
  CSR_PMPADDR0       = 0x3b0, 
  CSR_PMPADDR1       = 0x3b1, 
  CSR_PMPADDR2       = 0x3b2, 
  CSR_PMPADDR3       = 0x3b3, 
  CSR_PMPADDR4       = 0x3b4, 
  CSR_PMPADDR5       = 0x3b5, 
  CSR_PMPADDR6       = 0x3b6, 
  CSR_PMPADDR7       = 0x3b7, 
  CSR_PMPADDR8       = 0x3b8, 
  CSR_PMPADDR9       = 0x3b9, 
  CSR_PMPADDR10      = 0x3ba, 
  CSR_PMPADDR11      = 0x3bb, 
  CSR_PMPADDR12      = 0x3bc, 
  CSR_PMPADDR13      = 0x3bd, 
  CSR_PMPADDR14      = 0x3be, 
  CSR_PMPADDR15      = 0x3bf, 
  /* on-chip debugger - hardware trigger module */
  CSR_TSELECT        = 0x7a0, 
  CSR_TDATA1         = 0x7a1, 
  CSR_TDATA2         = 0x7a2, 
  CSR_TDATA3         = 0x7a3, 
  CSR_TINFO          = 0x7a4, 
  CSR_TCONTROL       = 0x7a5, 
  CSR_MCONTEXT       = 0x7a8, 
  CSR_SCONTEXT       = 0x7aa, 
  /* not accessible by m-mode software */
//CSR_DCSR           = 0x7b0, /**< 0x7b0 - dcsr     (-/-): Debug status and control register */
//CSR_DPC            = 0x7b1, /**< 0x7b1 - dpc      (-/-): Debug program counter */
//CSR_DSCRATCH       = 0x7b2, /**< 0x7b2 - dscratch (-/-): Debug scratch register */
 
  /* counter and timers - low word */
  CSR_MCYCLE         = 0xb00, 
  CSR_MINSTRET       = 0xb02, 
  CSR_MHPMCOUNTER3   = 0xb03, 
  CSR_MHPMCOUNTER4   = 0xb04, 
  CSR_MHPMCOUNTER5   = 0xb05, 
  CSR_MHPMCOUNTER6   = 0xb06, 
  CSR_MHPMCOUNTER7   = 0xb07, 
  CSR_MHPMCOUNTER8   = 0xb08, 
  CSR_MHPMCOUNTER9   = 0xb09, 
  CSR_MHPMCOUNTER10  = 0xb0a, 
  CSR_MHPMCOUNTER11  = 0xb0b, 
  CSR_MHPMCOUNTER12  = 0xb0c, 
  CSR_MHPMCOUNTER13  = 0xb0d, 
  CSR_MHPMCOUNTER14  = 0xb0e, 
  CSR_MHPMCOUNTER15  = 0xb0f, 
  CSR_MHPMCOUNTER16  = 0xb10, 
  CSR_MHPMCOUNTER17  = 0xb11, 
  CSR_MHPMCOUNTER18  = 0xb12, 
  CSR_MHPMCOUNTER19  = 0xb13, 
  CSR_MHPMCOUNTER20  = 0xb14, 
  CSR_MHPMCOUNTER21  = 0xb15, 
  CSR_MHPMCOUNTER22  = 0xb16, 
  CSR_MHPMCOUNTER23  = 0xb17, 
  CSR_MHPMCOUNTER24  = 0xb18, 
  CSR_MHPMCOUNTER25  = 0xb19, 
  CSR_MHPMCOUNTER26  = 0xb1a, 
  CSR_MHPMCOUNTER27  = 0xb1b, 
  CSR_MHPMCOUNTER28  = 0xb1c, 
  CSR_MHPMCOUNTER29  = 0xb1d, 
  CSR_MHPMCOUNTER30  = 0xb1e, 
  CSR_MHPMCOUNTER31  = 0xb1f, 
  CSR_MCYCLEH        = 0xb80, 
  CSR_MINSTRETH      = 0xb82, 
  CSR_MHPMCOUNTER3H  = 0xb83, 
  CSR_MHPMCOUNTER4H  = 0xb84, 
  CSR_MHPMCOUNTER5H  = 0xb85, 
  CSR_MHPMCOUNTER6H  = 0xb86, 
  CSR_MHPMCOUNTER7H  = 0xb87, 
  CSR_MHPMCOUNTER8H  = 0xb88, 
  CSR_MHPMCOUNTER9H  = 0xb89, 
  CSR_MHPMCOUNTER10H = 0xb8a, 
  CSR_MHPMCOUNTER11H = 0xb8b, 
  CSR_MHPMCOUNTER12H = 0xb8c, 
  CSR_MHPMCOUNTER13H = 0xb8d, 
  CSR_MHPMCOUNTER14H = 0xb8e, 
  CSR_MHPMCOUNTER15H = 0xb8f, 
  CSR_MHPMCOUNTER16H = 0xb90, 
  CSR_MHPMCOUNTER17H = 0xb91, 
  CSR_MHPMCOUNTER18H = 0xb92, 
  CSR_MHPMCOUNTER19H = 0xb93, 
  CSR_MHPMCOUNTER20H = 0xb94, 
  CSR_MHPMCOUNTER21H = 0xb95, 
  CSR_MHPMCOUNTER22H = 0xb96, 
  CSR_MHPMCOUNTER23H = 0xb97, 
  CSR_MHPMCOUNTER24H = 0xb98, 
  CSR_MHPMCOUNTER25H = 0xb99, 
  CSR_MHPMCOUNTER26H = 0xb9a, 
  CSR_MHPMCOUNTER27H = 0xb9b, 
  CSR_MHPMCOUNTER28H = 0xb9c, 
  CSR_MHPMCOUNTER29H = 0xb9d, 
  CSR_MHPMCOUNTER30H = 0xb9e, 
  CSR_MHPMCOUNTER31H = 0xb9f, 
  CSR_CYCLE          = 0xc00, 
  CSR_TIME           = 0xc01, 
  CSR_INSTRET        = 0xc02, 
  /* not implemented */
//CSR_HPMCOUNTER3    = 0xc03, /**< 0xc03 - hpmcounter3  (r/-): User hardware performance monitor 3  counter low word */
//CSR_HPMCOUNTER4    = 0xc04, /**< 0xc04 - hpmcounter4  (r/-): User hardware performance monitor 4  counter low word */
//CSR_HPMCOUNTER5    = 0xc05, /**< 0xc05 - hpmcounter5  (r/-): User hardware performance monitor 5  counter low word */
//CSR_HPMCOUNTER6    = 0xc06, /**< 0xc06 - hpmcounter6  (r/-): User hardware performance monitor 6  counter low word */
//CSR_HPMCOUNTER7    = 0xc07, /**< 0xc07 - hpmcounter7  (r/-): User hardware performance monitor 7  counter low word */
//CSR_HPMCOUNTER8    = 0xc08, /**< 0xc08 - hpmcounter8  (r/-): User hardware performance monitor 8  counter low word */
//CSR_HPMCOUNTER9    = 0xc09, /**< 0xc09 - hpmcounter9  (r/-): User hardware performance monitor 9  counter low word */
//CSR_HPMCOUNTER10   = 0xc0a, /**< 0xc0a - hpmcounter10 (r/-): User hardware performance monitor 10 counter low word */
//CSR_HPMCOUNTER11   = 0xc0b, /**< 0xc0b - hpmcounter11 (r/-): User hardware performance monitor 11 counter low word */
//CSR_HPMCOUNTER12   = 0xc0c, /**< 0xc0c - hpmcounter12 (r/-): User hardware performance monitor 12 counter low word */
//CSR_HPMCOUNTER13   = 0xc0d, /**< 0xc0d - hpmcounter13 (r/-): User hardware performance monitor 13 counter low word */
//CSR_HPMCOUNTER14   = 0xc0e, /**< 0xc0e - hpmcounter14 (r/-): User hardware performance monitor 14 counter low word */
//CSR_HPMCOUNTER15   = 0xc0f, /**< 0xc0f - hpmcounter15 (r/-): User hardware performance monitor 15 counter low word */
//CSR_HPMCOUNTER16   = 0xc10, /**< 0xc10 - hpmcounter16 (r/-): User hardware performance monitor 16 counter low word */
//CSR_HPMCOUNTER17   = 0xc11, /**< 0xc11 - hpmcounter17 (r/-): User hardware performance monitor 17 counter low word */
//CSR_HPMCOUNTER18   = 0xc12, /**< 0xc12 - hpmcounter18 (r/-): User hardware performance monitor 18 counter low word */
//CSR_HPMCOUNTER19   = 0xc13, /**< 0xc13 - hpmcounter19 (r/-): User hardware performance monitor 19 counter low word */
//CSR_HPMCOUNTER20   = 0xc14, /**< 0xc14 - hpmcounter20 (r/-): User hardware performance monitor 20 counter low word */
//CSR_HPMCOUNTER21   = 0xc15, /**< 0xc15 - hpmcounter21 (r/-): User hardware performance monitor 21 counter low word */
//CSR_HPMCOUNTER22   = 0xc16, /**< 0xc16 - hpmcounter22 (r/-): User hardware performance monitor 22 counter low word */
//CSR_HPMCOUNTER23   = 0xc17, /**< 0xc17 - hpmcounter23 (r/-): User hardware performance monitor 23 counter low word */
//CSR_HPMCOUNTER24   = 0xc18, /**< 0xc18 - hpmcounter24 (r/-): User hardware performance monitor 24 counter low word */
//CSR_HPMCOUNTER25   = 0xc19, /**< 0xc19 - hpmcounter25 (r/-): User hardware performance monitor 25 counter low word */
//CSR_HPMCOUNTER26   = 0xc1a, /**< 0xc1a - hpmcounter26 (r/-): User hardware performance monitor 26 counter low word */
//CSR_HPMCOUNTER27   = 0xc1b, /**< 0xc1b - hpmcounter27 (r/-): User hardware performance monitor 27 counter low word */
//CSR_HPMCOUNTER28   = 0xc1c, /**< 0xc1c - hpmcounter28 (r/-): User hardware performance monitor 28 counter low word */
//CSR_HPMCOUNTER29   = 0xc1d, /**< 0xc1d - hpmcounter29 (r/-): User hardware performance monitor 29 counter low word */
//CSR_HPMCOUNTER30   = 0xc1e, /**< 0xc1e - hpmcounter30 (r/-): User hardware performance monitor 30 counter low word */
//CSR_HPMCOUNTER31   = 0xc1f, /**< 0xc1f - hpmcounter31 (r/-): User hardware performance monitor 31 counter low word */
 
 
  /* counter and timers - high word */
  CSR_CYCLEH         = 0xc80, 
  CSR_TIMEH          = 0xc81, 
  CSR_INSTRETH       = 0xc82, 
  /* not implemented */
//CSR_HPMCOUNTER3H   = 0xc83, /**< 0xc83 - hpmcounter3h  (r/-): User hardware performance monitor 3  counter high word */
//CSR_HPMCOUNTER4H   = 0xc84, /**< 0xc84 - hpmcounter4h  (r/-): User hardware performance monitor 4  counter high word */
//CSR_HPMCOUNTER5H   = 0xc85, /**< 0xc85 - hpmcounter5h  (r/-): User hardware performance monitor 5  counter high word */
//CSR_HPMCOUNTER6H   = 0xc86, /**< 0xc86 - hpmcounter6h  (r/-): User hardware performance monitor 6  counter high word */
//CSR_HPMCOUNTER7H   = 0xc87, /**< 0xc87 - hpmcounter7h  (r/-): User hardware performance monitor 7  counter high word */
//CSR_HPMCOUNTER8H   = 0xc88, /**< 0xc88 - hpmcounter8h  (r/-): User hardware performance monitor 8  counter high word */
//CSR_HPMCOUNTER9H   = 0xc89, /**< 0xc89 - hpmcounter9h  (r/-): User hardware performance monitor 9  counter high word */
//CSR_HPMCOUNTER10H  = 0xc8a, /**< 0xc8a - hpmcounter10h (r/-): User hardware performance monitor 10 counter high word */
//CSR_HPMCOUNTER11H  = 0xc8b, /**< 0xc8b - hpmcounter11h (r/-): User hardware performance monitor 11 counter high word */
//CSR_HPMCOUNTER12H  = 0xc8c, /**< 0xc8c - hpmcounter12h (r/-): User hardware performance monitor 12 counter high word */
//CSR_HPMCOUNTER13H  = 0xc8d, /**< 0xc8d - hpmcounter13h (r/-): User hardware performance monitor 13 counter high word */
//CSR_HPMCOUNTER14H  = 0xc8e, /**< 0xc8e - hpmcounter14h (r/-): User hardware performance monitor 14 counter high word */
//CSR_HPMCOUNTER15H  = 0xc8f, /**< 0xc8f - hpmcounter15h (r/-): User hardware performance monitor 15 counter high word */
//CSR_HPMCOUNTER16H  = 0xc90, /**< 0xc90 - hpmcounter16h (r/-): User hardware performance monitor 16 counter high word */
//CSR_HPMCOUNTER17H  = 0xc91, /**< 0xc91 - hpmcounter17h (r/-): User hardware performance monitor 17 counter high word */
//CSR_HPMCOUNTER18H  = 0xc92, /**< 0xc92 - hpmcounter18h (r/-): User hardware performance monitor 18 counter high word */
//CSR_HPMCOUNTER19H  = 0xc93, /**< 0xc93 - hpmcounter19h (r/-): User hardware performance monitor 19 counter high word */
//CSR_HPMCOUNTER20H  = 0xc94, /**< 0xc94 - hpmcounter20h (r/-): User hardware performance monitor 20 counter high word */
//CSR_HPMCOUNTER21H  = 0xc95, /**< 0xc95 - hpmcounter21h (r/-): User hardware performance monitor 21 counter high word */
//CSR_HPMCOUNTER22H  = 0xc96, /**< 0xc96 - hpmcounter22h (r/-): User hardware performance monitor 22 counter high word */
//CSR_HPMCOUNTER23H  = 0xc97, /**< 0xc97 - hpmcounter23h (r/-): User hardware performance monitor 23 counter high word */
//CSR_HPMCOUNTER24H  = 0xc98, /**< 0xc98 - hpmcounter24h (r/-): User hardware performance monitor 24 counter high word */
//CSR_HPMCOUNTER25H  = 0xc99, /**< 0xc99 - hpmcounter25h (r/-): User hardware performance monitor 25 counter high word */
//CSR_HPMCOUNTER26H  = 0xc9a, /**< 0xc9a - hpmcounter26h (r/-): User hardware performance monitor 26 counter high word */
//CSR_HPMCOUNTER27H  = 0xc9b, /**< 0xc9b - hpmcounter27h (r/-): User hardware performance monitor 27 counter high word */
//CSR_HPMCOUNTER28H  = 0xc9c, /**< 0xc9c - hpmcounter28h (r/-): User hardware performance monitor 28 counter high word */
//CSR_HPMCOUNTER29H  = 0xc9d, /**< 0xc9d - hpmcounter29h (r/-): User hardware performance monitor 29 counter high word */
//CSR_HPMCOUNTER30H  = 0xc9e, /**< 0xc9e - hpmcounter30h (r/-): User hardware performance monitor 30 counter high word */
//CSR_HPMCOUNTER31H  = 0xc9f, /**< 0xc9f - hpmcounter31h (r/-): User hardware performance monitor 31 counter high word */
 
  /* machine information registers */
  CSR_MVENDORID      = 0xf11, 
  CSR_MARCHID        = 0xf12, 
  CSR_MIMPID         = 0xf13, 
  CSR_MHARTID        = 0xf14, 
  CSR_MCONFIGPTR     = 0xf15, 
  CSR_MXISA          = 0xfc0  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MSTATUS_enum {
  CSR_MSTATUS_MIE   =  3, 
  CSR_MSTATUS_MPIE  =  7, 
  CSR_MSTATUS_MPP_L = 11, 
  CSR_MSTATUS_MPP_H = 12, 
  CSR_MSTATUS_TW    = 21  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MCOUNTEREN_enum {
  CSR_MCOUNTEREN_CY    = 0, 
  CSR_MCOUNTEREN_TM    = 1, 
  CSR_MCOUNTEREN_IR    = 2  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MCOUNTINHIBIT_enum {
  CSR_MCOUNTINHIBIT_CY    = 0,  
  CSR_MCOUNTINHIBIT_IR    = 2,  
  CSR_MCOUNTINHIBIT_HPM3  = 3,  
  CSR_MCOUNTINHIBIT_HPM4  = 4,  
  CSR_MCOUNTINHIBIT_HPM5  = 5,  
  CSR_MCOUNTINHIBIT_HPM6  = 6,  
  CSR_MCOUNTINHIBIT_HPM7  = 7,  
  CSR_MCOUNTINHIBIT_HPM8  = 8,  
  CSR_MCOUNTINHIBIT_HPM9  = 9,  
  CSR_MCOUNTINHIBIT_HPM10 = 10, 
  CSR_MCOUNTINHIBIT_HPM11 = 11, 
  CSR_MCOUNTINHIBIT_HPM12 = 12, 
  CSR_MCOUNTINHIBIT_HPM13 = 13, 
  CSR_MCOUNTINHIBIT_HPM14 = 14, 
  CSR_MCOUNTINHIBIT_HPM15 = 15, 
  CSR_MCOUNTINHIBIT_HPM16 = 16, 
  CSR_MCOUNTINHIBIT_HPM17 = 17, 
  CSR_MCOUNTINHIBIT_HPM18 = 18, 
  CSR_MCOUNTINHIBIT_HPM19 = 19, 
  CSR_MCOUNTINHIBIT_HPM20 = 20, 
  CSR_MCOUNTINHIBIT_HPM21 = 21, 
  CSR_MCOUNTINHIBIT_HPM22 = 22, 
  CSR_MCOUNTINHIBIT_HPM23 = 23, 
  CSR_MCOUNTINHIBIT_HPM24 = 24, 
  CSR_MCOUNTINHIBIT_HPM25 = 25, 
  CSR_MCOUNTINHIBIT_HPM26 = 26, 
  CSR_MCOUNTINHIBIT_HPM27 = 27, 
  CSR_MCOUNTINHIBIT_HPM28 = 28, 
  CSR_MCOUNTINHIBIT_HPM29 = 29, 
  CSR_MCOUNTINHIBIT_HPM30 = 30, 
  CSR_MCOUNTINHIBIT_HPM31 = 31  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MIE_enum {
  CSR_MIE_MSIE    =  3, 
  CSR_MIE_MTIE    =  7, 
  CSR_MIE_MEIE    = 11, 
  CSR_MIE_FIRQ0E  = 16, 
  CSR_MIE_FIRQ1E  = 17, 
  CSR_MIE_FIRQ2E  = 18, 
  CSR_MIE_FIRQ3E  = 19, 
  CSR_MIE_FIRQ4E  = 20, 
  CSR_MIE_FIRQ5E  = 21, 
  CSR_MIE_FIRQ6E  = 22, 
  CSR_MIE_FIRQ7E  = 23, 
  CSR_MIE_FIRQ8E  = 24, 
  CSR_MIE_FIRQ9E  = 25, 
  CSR_MIE_FIRQ10E = 26, 
  CSR_MIE_FIRQ11E = 27, 
  CSR_MIE_FIRQ12E = 28, 
  CSR_MIE_FIRQ13E = 29, 
  CSR_MIE_FIRQ14E = 30, 
  CSR_MIE_FIRQ15E = 31  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MIP_enum {
  CSR_MIP_MSIP    =  3, 
  CSR_MIP_MTIP    =  7, 
  CSR_MIP_MEIP    = 11, 
  /* NEORV32-specific extension */
  CSR_MIP_FIRQ0P  = 16, 
  CSR_MIP_FIRQ1P  = 17, 
  CSR_MIP_FIRQ2P  = 18, 
  CSR_MIP_FIRQ3P  = 19, 
  CSR_MIP_FIRQ4P  = 20, 
  CSR_MIP_FIRQ5P  = 21, 
  CSR_MIP_FIRQ6P  = 22, 
  CSR_MIP_FIRQ7P  = 23, 
  CSR_MIP_FIRQ8P  = 24, 
  CSR_MIP_FIRQ9P  = 25, 
  CSR_MIP_FIRQ10P = 26, 
  CSR_MIP_FIRQ11P = 27, 
  CSR_MIP_FIRQ12P = 28, 
  CSR_MIP_FIRQ13P = 29, 
  CSR_MIP_FIRQ14P = 30, 
  CSR_MIP_FIRQ15P = 31  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_MISA_enum {
  CSR_MISA_A      =  0, 
  CSR_MISA_B      =  1, 
  CSR_MISA_C      =  2, 
  CSR_MISA_D      =  3, 
  CSR_MISA_E      =  4, 
  CSR_MISA_F      =  5, 
  CSR_MISA_I      =  8, 
  CSR_MISA_M      = 12, 
  CSR_MISA_U      = 20, 
  CSR_MISA_X      = 23, 
  CSR_MISA_MXL_LO = 30, 
  CSR_MISA_MXL_HI = 31  
};
 
 
/**********************************************************************/
enum NEORV32_CSR_XISA_enum {
  // ISA (sub-)extensions
  CSR_MXISA_ZICSR     =  0, 
  CSR_MXISA_ZIFENCEI  =  1, 
  CSR_MXISA_ZMMUL     =  2, 
  CSR_MXISA_ZXCFU     =  3, 
  CSR_MXISA_ZFINX     =  5, 
  CSR_MXISA_ZXSCNT    =  6, 
  CSR_MXISA_ZICNTR    =  7, 
  CSR_MXISA_PMP       =  8, 
  CSR_MXISA_ZIHPM     =  9, 
  CSR_MXISA_DEBUGMODE = 10, 
  // Misc
  CSR_MXISA_IS_SIM    = 20, 
  CSR_MXISA_HW_RESET  = 21, 
  // Tuning options
  CSR_MXISA_FASTMUL   = 30, 
  CSR_MXISA_FASTSHIFT = 31  
};
 
 
/**********************************************************************/
enum NEORV32_HPMCNT_EVENT_enum {
  HPMCNT_EVENT_CY      = 0,  
  HPMCNT_EVENT_IR      = 2,  
  HPMCNT_EVENT_CIR     = 3,  
  HPMCNT_EVENT_WAIT_IF = 4,  
  HPMCNT_EVENT_WAIT_II = 5,  
  HPMCNT_EVENT_WAIT_MC = 6,  
  HPMCNT_EVENT_LOAD    = 7,  
  HPMCNT_EVENT_STORE   = 8,  
  HPMCNT_EVENT_WAIT_LS = 9,  
  HPMCNT_EVENT_JUMP    = 10, 
  HPMCNT_EVENT_BRANCH  = 11, 
  HPMCNT_EVENT_TBRANCH = 12, 
  HPMCNT_EVENT_TRAP    = 13, 
  HPMCNT_EVENT_ILLEGAL = 14  
};
 
 
/**********************************************************************/
enum NEORV32_PMPCFG_ATTRIBUTES_enum {
  PMPCFG_R     = 0, 
  PMPCFG_W     = 1, 
  PMPCFG_X     = 2, 
  PMPCFG_A_LSB = 3, 
  PMPCFG_A_MSB = 4, 
  PMPCFG_L     = 7  
};
 
/**********************************************************************/
enum NEORV32_PMP_MODES_enum {
  PMP_OFF = 0, 
  PMP_TOR = 1  
};
 
 
/**********************************************************************/
enum NEORV32_EXCEPTION_CODES_enum {
  TRAP_CODE_I_MISALIGNED = 0x00000000UL, 
  TRAP_CODE_I_ACCESS     = 0x00000001UL, 
  TRAP_CODE_I_ILLEGAL    = 0x00000002UL, 
  TRAP_CODE_BREAKPOINT   = 0x00000003UL, 
  TRAP_CODE_L_MISALIGNED = 0x00000004UL, 
  TRAP_CODE_L_ACCESS     = 0x00000005UL, 
  TRAP_CODE_S_MISALIGNED = 0x00000006UL, 
  TRAP_CODE_S_ACCESS     = 0x00000007UL, 
  TRAP_CODE_UENV_CALL    = 0x00000008UL, 
  TRAP_CODE_MENV_CALL    = 0x0000000bUL, 
  TRAP_CODE_MSI          = 0x80000003UL, 
  TRAP_CODE_MTI          = 0x80000007UL, 
  TRAP_CODE_MEI          = 0x8000000bUL, 
  TRAP_CODE_FIRQ_0       = 0x80000010UL, 
  TRAP_CODE_FIRQ_1       = 0x80000011UL, 
  TRAP_CODE_FIRQ_2       = 0x80000012UL, 
  TRAP_CODE_FIRQ_3       = 0x80000013UL, 
  TRAP_CODE_FIRQ_4       = 0x80000014UL, 
  TRAP_CODE_FIRQ_5       = 0x80000015UL, 
  TRAP_CODE_FIRQ_6       = 0x80000016UL, 
  TRAP_CODE_FIRQ_7       = 0x80000017UL, 
  TRAP_CODE_FIRQ_8       = 0x80000018UL, 
  TRAP_CODE_FIRQ_9       = 0x80000019UL, 
  TRAP_CODE_FIRQ_10      = 0x8000001aUL, 
  TRAP_CODE_FIRQ_11      = 0x8000001bUL, 
  TRAP_CODE_FIRQ_12      = 0x8000001cUL, 
  TRAP_CODE_FIRQ_13      = 0x8000001dUL, 
  TRAP_CODE_FIRQ_14      = 0x8000001eUL, 
  TRAP_CODE_FIRQ_15      = 0x8000001fUL  
};
 
 
/**********************************************************************/
enum NEORV32_CLOCK_PRSC_enum {
  CLK_PRSC_2    = 0, 
  CLK_PRSC_4    = 1, 
  CLK_PRSC_8    = 2, 
  CLK_PRSC_64   = 3, 
  CLK_PRSC_128  = 4, 
  CLK_PRSC_1024 = 5, 
  CLK_PRSC_2048 = 6, 
  CLK_PRSC_4096 = 7  
};
 
 
/**********************************************************************/
#define NEORV32_ARCHID 19
 
 
/**********************************************************************/
#define WDT_FIRQ_ENABLE        CSR_MIE_FIRQ0E    
#define WDT_FIRQ_PENDING       CSR_MIP_FIRQ0P    
#define WDT_RTE_ID             RTE_TRAP_FIRQ_0   
#define WDT_TRAP_CODE          TRAP_CODE_FIRQ_0  
#define CFS_FIRQ_ENABLE        CSR_MIE_FIRQ1E    
#define CFS_FIRQ_PENDING       CSR_MIP_FIRQ1P    
#define CFS_RTE_ID             RTE_TRAP_FIRQ_1   
#define CFS_TRAP_CODE          TRAP_CODE_FIRQ_1  
#define UART0_RX_FIRQ_ENABLE   CSR_MIE_FIRQ2E    
#define UART0_RX_FIRQ_PENDING  CSR_MIP_FIRQ2P    
#define UART0_RX_RTE_ID        RTE_TRAP_FIRQ_2   
#define UART0_RX_TRAP_CODE     TRAP_CODE_FIRQ_2  
#define UART0_TX_FIRQ_ENABLE   CSR_MIE_FIRQ3E    
#define UART0_TX_FIRQ_PENDING  CSR_MIP_FIRQ3P    
#define UART0_TX_RTE_ID        RTE_TRAP_FIRQ_3   
#define UART0_TX_TRAP_CODE     TRAP_CODE_FIRQ_4  
#define UART1_RX_FIRQ_ENABLE   CSR_MIE_FIRQ4E    
#define UART1_RX_FIRQ_PENDING  CSR_MIP_FIRQ4P    
#define UART1_RX_RTE_ID        RTE_TRAP_FIRQ_4   
#define UART1_RX_TRAP_CODE     TRAP_CODE_FIRQ_4  
#define UART1_TX_FIRQ_ENABLE   CSR_MIE_FIRQ5E    
#define UART1_TX_FIRQ_PENDING  CSR_MIP_FIRQ5P    
#define UART1_TX_RTE_ID        RTE_TRAP_FIRQ_5   
#define UART1_TX_TRAP_CODE     TRAP_CODE_FIRQ_5  
#define SPI_FIRQ_ENABLE        CSR_MIE_FIRQ6E    
#define SPI_FIRQ_PENDING       CSR_MIP_FIRQ6P    
#define SPI_RTE_ID             RTE_TRAP_FIRQ_6   
#define SPI_TRAP_CODE          TRAP_CODE_FIRQ_6  
#define TWI_FIRQ_ENABLE        CSR_MIE_FIRQ7E    
#define TWI_FIRQ_PENDING       CSR_MIP_FIRQ7P    
#define TWI_RTE_ID             RTE_TRAP_FIRQ_7   
#define TWI_TRAP_CODE          TRAP_CODE_FIRQ_7  
#define XIRQ_FIRQ_ENABLE       CSR_MIE_FIRQ8E    
#define XIRQ_FIRQ_PENDING      CSR_MIP_FIRQ8P    
#define XIRQ_RTE_ID            RTE_TRAP_FIRQ_8   
#define XIRQ_TRAP_CODE         TRAP_CODE_FIRQ_8  
#define NEOLED_FIRQ_ENABLE     CSR_MIE_FIRQ9E    
#define NEOLED_FIRQ_PENDING    CSR_MIP_FIRQ9P    
#define NEOLED_RTE_ID          RTE_TRAP_FIRQ_9   
#define NEOLED_TRAP_CODE       TRAP_CODE_FIRQ_9  
#define SLINK_RX_FIRQ_ENABLE   CSR_MIE_FIRQ10E   
#define SLINK_RX_FIRQ_PENDING  CSR_MIP_FIRQ10P   
#define SLINK_RX_RTE_ID        RTE_TRAP_FIRQ_10  
#define SLINK_RX_TRAP_CODE     TRAP_CODE_FIRQ_10 
#define SLINK_TX_FIRQ_ENABLE   CSR_MIE_FIRQ11E   
#define SLINK_TX_FIRQ_PENDING  CSR_MIP_FIRQ11P   
#define SLINK_TX_RTE_ID        RTE_TRAP_FIRQ_11  
#define SLINK_TX_TRAP_CODE     TRAP_CODE_FIRQ_11 
#define GPTMR_FIRQ_ENABLE      CSR_MIE_FIRQ12E   
#define GPTMR_FIRQ_PENDING     CSR_MIP_FIRQ12P   
#define GPTMR_RTE_ID           RTE_TRAP_FIRQ_12  
#define GPTMR_TRAP_CODE        TRAP_CODE_FIRQ_12 
/**********************************************************************/
// -> configured via 'ispace_base_c' constant in neorv32_package.vhd and available to software via SYSINFO entry
// -> configured via 'dspace_base_c' constant in neorv32_package.vhd and available to software via SYSINFO entry
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
#define OCD_BASE_ADDRESS        (0XFFFFF800UL)
#define IO_BASE_ADDRESS         (0xFFFFFE00UL)
// ############################################################################################################################
// On-Chip Debugger (should NOT be used by application software at all!)
// ############################################################################################################################
typedef struct __attribute__((packed,aligned(4))) {
  const uint32_t CODE[32];      
  const uint32_t PBUF[4];       
  const uint32_t reserved1[28]; 
  uint32_t       DATA;          
  const uint32_t reserved2[31]; 
  uint32_t       SREG;          
  const uint32_t reserved3[31]; 
} neorv32_dm_t;
 
#define NEORV32_DM_BASE (0XFFFFF800UL)
 
#define NEORV32_DM (*((volatile neorv32_dm_t*) (NEORV32_DM_BASE)))
 
enum NEORV32_OCD_DM_SREG_enum {
  OCD_DM_SREG_HALT_ACK      = 0, 
  OCD_DM_SREG_RESUME_REQ    = 1, 
  OCD_DM_SREG_RESUME_ACK    = 2, 
  OCD_DM_SREG_EXECUTE_REQ   = 3, 
  OCD_DM_SREG_EXECUTE_ACK   = 4, 
  OCD_DM_SREG_EXCEPTION_ACK = 5  
};
// ############################################################################################################################
// Peripheral/IO Devices - IO Address Space
// ############################################################################################################################
 
 
/**********************************************************************/
#define IO_REG8  (volatile uint8_t*)
#define IO_REG16 (volatile uint16_t*)
#define IO_REG32 (volatile uint32_t*)
#define IO_REG64 (volatile uint64_t*)
#define IO_ROM8  (const volatile uint8_t*) 
#define IO_ROM16 (const volatile uint16_t*)
#define IO_ROM32 (const volatile uint32_t*)
#define IO_ROM64 (const volatile uint64_t*)
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t REG[32]; 
} neorv32_cfs_t;
 
#define NEORV32_CFS_BASE (0xFFFFFE00UL)
 
#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (NEORV32_CFS_BASE)))
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;     
  uint32_t DUTY[15]; 
} neorv32_pwm_t;
 
#define NEORV32_PWM_BASE (0xFFFFFE80UL)
 
#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (NEORV32_PWM_BASE)))
 
enum NEORV32_PWM_CTRL_enum {
  PWM_CTRL_EN    =  0, 
  PWM_CTRL_PRSC0 =  1, 
  PWM_CTRL_PRSC1 =  2, 
  PWM_CTRL_PRSC2 =  3  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t       CTRL;          
  const uint32_t reserved0[3];  
  uint32_t       STATUS;        
  const uint32_t reserved1[3];  
  uint32_t       DATA[8];       
} neorv32_slink_t;
 
#define NEORV32_SLINK_BASE (0xFFFFFEC0UL)
 
#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (NEORV32_SLINK_BASE)))
 
enum NEORV32_SLINK_CTRL_enum {
  SLINK_CTRL_EN            =  0, 
  SLINK_CTRL_RX_FIFO_S0    =  8, 
  SLINK_CTRL_RX_FIFO_S1    =  9, 
  SLINK_CTRL_RX_FIFO_S2    = 10, 
  SLINK_CTRL_RX_FIFO_S3    = 11, 
  SLINK_CTRL_TX_FIFO_S0    = 12, 
  SLINK_CTRL_TX_FIFO_S1    = 13, 
  SLINK_CTRL_TX_FIFO_S2    = 14, 
  SLINK_CTRL_TX_FIFO_S3    = 15, 
  SLINK_CTRL_RX_IRQ_EN_LSB = 16, 
  SLINK_CTRL_RX_IRQ_EN_MSB = 23, 
  SLINK_CTRL_TX_IRQ_EN_LSB = 24, 
  SLINK_CTRL_TX_IRQ_EN_MSB = 31  
};
 
enum NEORV32_SLINK_STATUS_enum {
  SLINK_STATUS_RX_AVAIL_LSB =  0, 
  SLINK_STATUS_RX_AVAIL_MSB =  7, 
  SLINK_STATUS_TX_FREE_LSB  =  8, 
  SLINK_STATUS_TX_FREE_MSB  = 15, 
  SLINK_STATUS_RX_LAST_LSB  = 16, 
  SLINK_STATUS_RX_LAST_MSB  = 23, 
  SLINK_STATUS_TX_LAST_LSB  = 24, 
  SLINK_STATUS_TX_LAST_MSB  = 31, 
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;           
  const uint32_t reserved; 
  uint32_t DATA_LO;        
  uint32_t DATA_HI;        
} neorv32_xip_t;
 
#define NEORV32_XIP_BASE (0xFFFFFF40UL)
 
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (NEORV32_XIP_BASE)))
 
enum NEORV32_XIP_CTRL_enum {
  XIP_CTRL_EN             =  0, 
  XIP_CTRL_PRSC0          =  1, 
  XIP_CTRL_PRSC1          =  2, 
  XIP_CTRL_PRSC2          =  3, 
  XIP_CTRL_CPOL           =  4, 
  XIP_CTRL_CPHA           =  5, 
  XIP_CTRL_SPI_NBYTES_LSB =  6, 
  XIP_CTRL_SPI_NBYTES_MSB =  9, 
  XIP_CTRL_XIP_EN         = 10, 
  XIP_CTRL_XIP_ABYTES_LSB = 11, 
  XIP_CTRL_XIP_ABYTES_MSB = 12, 
  XIP_CTRL_RD_CMD_LSB     = 13, 
  XIP_CTRL_RD_CMD_MSB     = 20, 
  XIP_CTRL_PAGE_LSB       = 21, 
  XIP_CTRL_PAGE_MSB       = 24, 
  XIP_CTRL_SPI_CSEN       = 25, 
  XIP_CTRL_HIGHSPEED      = 26, 
  XIP_CTRL_PHY_BUSY       = 30, 
  XIP_CTRL_XIP_BUSY       = 31  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;           
  uint32_t THRES;          
  uint32_t COUNT;          
  const uint32_t reserved; 
} neorv32_gptmr_t;
 
#define NEORV32_GPTMR_BASE (0xFFFFFF60UL)
 
#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (NEORV32_GPTMR_BASE)))
 
enum NEORV32_GPTMR_CTRL_enum {
  GPTMR_CTRL_EN    = 0, 
  GPTMR_CTRL_PRSC0 = 1, 
  GPTMR_CTRL_PRSC1 = 2, 
  GPTMR_CTRL_PRSC2 = 3, 
  GPTMR_CTRL_MODE  = 4  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL; 
} neorv32_buskeeper_t;
 
#define NEORV32_BUSKEEPER_BASE (0xFFFFFF7CUL)
 
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE)))
 
enum NEORV32_BUSKEEPER_CTRL_enum {
  BUSKEEPER_ERR_TYPE =  0, 
  BUSKEEPER_ERR_FLAG = 31  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t       IER;      
  uint32_t       IPR;      
  uint32_t       SCR;      
  const uint32_t reserved; 
} neorv32_xirq_t;
 
#define NEORV32_XIRQ_BASE (0xFFFFFF80UL)
 
#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (NEORV32_XIRQ_BASE)))
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t TIME_LO;    
  uint32_t TIME_HI;    
  uint32_t TIMECMP_LO; 
  uint32_t TIMECMP_HI; 
} neorv32_mtime_t;
 
#define NEORV32_MTIME_BASE (0xFFFFFF90UL)
 
#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (NEORV32_MTIME_BASE)))
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;  
  uint32_t DATA;  
} neorv32_uart0_t;
 
#define NEORV32_UART0_BASE (0xFFFFFFA0UL)
 
#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (NEORV32_UART0_BASE)))
 
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;  
  uint32_t DATA;  
} neorv32_uart1_t;
 
#define NEORV32_UART1_BASE (0xFFFFFFD0UL)
 
#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (NEORV32_UART1_BASE)))
 
enum NEORV32_UART_CTRL_enum {
  UART_CTRL_BAUD00   =  0, 
  UART_CTRL_BAUD01   =  1, 
  UART_CTRL_BAUD02   =  2, 
  UART_CTRL_BAUD03   =  3, 
  UART_CTRL_BAUD04   =  4, 
  UART_CTRL_BAUD05   =  5, 
  UART_CTRL_BAUD06   =  6, 
  UART_CTRL_BAUD07   =  7, 
  UART_CTRL_BAUD08   =  8, 
  UART_CTRL_BAUD09   =  9, 
  UART_CTRL_BAUD10   = 10, 
  UART_CTRL_BAUD11   = 11, 
  UART_CTRL_SIM_MODE = 12, 
  UART_CTRL_RX_EMPTY = 13, 
  UART_CTRL_RX_HALF  = 14, 
  UART_CTRL_RX_FULL  = 15, 
  UART_CTRL_TX_EMPTY = 16, 
  UART_CTRL_TX_HALF  = 17, 
  UART_CTRL_TX_FULL  = 18, 
  UART_CTRL_RTS_EN   = 20, 
  UART_CTRL_CTS_EN   = 21, 
  UART_CTRL_PMODE0   = 22, 
  UART_CTRL_PMODE1   = 23, 
  UART_CTRL_PRSC0    = 24, 
  UART_CTRL_PRSC1    = 25, 
  UART_CTRL_PRSC2    = 26, 
  UART_CTRL_CTS      = 27, 
  UART_CTRL_EN       = 28, 
  UART_CTRL_RX_IRQ   = 29, 
  UART_CTRL_TX_IRQ   = 30, 
  UART_CTRL_TX_BUSY  = 31  
};
 
enum NEORV32_UART_PARITY_enum {
  PARITY_NONE = 0b00, 
  PARITY_EVEN = 0b10, 
  PARITY_ODD  = 0b11  
};
 
enum NEORV32_UART_FLOW_CONTROL_enum {
  FLOW_CONTROL_NONE   = 0b00, 
  FLOW_CONTROL_RTS    = 0b01, 
  FLOW_CONTROL_CTS    = 0b10, 
  FLOW_CONTROL_RTSCTS = 0b11  
};
 
enum NEORV32_UART_DATA_enum {
  UART_DATA_LSB   =  0, 
  UART_DATA_MSB   =  7, 
  UART_DATA_PERR  = 28, 
  UART_DATA_FERR  = 29, 
  UART_DATA_OVERR = 30, 
  UART_DATA_AVAIL = 31  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;  
  uint32_t DATA;  
} neorv32_spi_t;
 
#define NEORV32_SPI_BASE (0xFFFFFFA8UL)
 
#define NEORV32_SPI (*((volatile neorv32_spi_t*) (NEORV32_SPI_BASE)))
 
enum NEORV32_SPI_CTRL_enum {
  SPI_CTRL_CS0       =  0, 
  SPI_CTRL_CS1       =  1, 
  SPI_CTRL_CS2       =  2, 
  SPI_CTRL_CS3       =  3, 
  SPI_CTRL_CS4       =  4, 
  SPI_CTRL_CS5       =  5, 
  SPI_CTRL_CS6       =  6, 
  SPI_CTRL_CS7       =  7, 
  SPI_CTRL_EN        =  8, 
  SPI_CTRL_CPHA      =  9, 
  SPI_CTRL_PRSC0     = 10, 
  SPI_CTRL_PRSC1     = 11, 
  SPI_CTRL_PRSC2     = 12, 
  SPI_CTRL_SIZE0     = 13, 
  SPI_CTRL_SIZE1     = 14, 
  SPI_CTRL_CPOL      = 15, 
  SPI_CTRL_HIGHSPEED = 16, 
  SPI_CTRL_BUSY      = 31  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;  
  uint32_t DATA;  
} neorv32_twi_t;
 
#define NEORV32_TWI_BASE (0xFFFFFFB0UL)
 
#define NEORV32_TWI (*((volatile neorv32_twi_t*) (NEORV32_TWI_BASE)))
 
enum NEORV32_TWI_CTRL_enum {
  TWI_CTRL_EN      =  0, 
  TWI_CTRL_START   =  1, 
  TWI_CTRL_STOP    =  2, 
  TWI_CTRL_PRSC0   =  3, 
  TWI_CTRL_PRSC1   =  4, 
  TWI_CTRL_PRSC2   =  5, 
  TWI_CTRL_MACK    =  6, 
  TWI_CTRL_CLAIMED = 29, 
  TWI_CTRL_ACK     = 30, 
  TWI_CTRL_BUSY    = 31  
};
 
enum NEORV32_TWI_DATA_enum {
  TWI_DATA_LSB = 0, 
  TWI_DATA_MSB = 7  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;  
} neorv32_trng_t;
 
#define NEORV32_TRNG_BASE (0xFFFFFFB8UL)
 
#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (NEORV32_TRNG_BASE)))
 
enum NEORV32_TRNG_CTRL_enum {
  TRNG_CTRL_DATA_LSB =  0, 
  TRNG_CTRL_DATA_MSB =  7, 
  TRNG_CTRL_FIFO_CLR = 28, 
  TRNG_CTRL_SIM_MODE = 29, 
  TRNG_CTRL_EN       = 30, 
  TRNG_CTRL_VALID    = 31  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;  
} neorv32_wdt_t;
 
#define NEORV32_WDT_BASE (0xFFFFFFBCUL)
 
#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (NEORV32_WDT_BASE)))
 
#define NEORV32_WDT_PWD (0xCA36)
 
enum NEORV32_WDT_CTRL_enum {
  WDT_CTRL_EN       =  0, 
  WDT_CTRL_CLK_SEL0 =  1, 
  WDT_CTRL_CLK_SEL1 =  2, 
  WDT_CTRL_CLK_SEL2 =  3, 
  WDT_CTRL_MODE     =  4, 
  WDT_CTRL_RCAUSE   =  5, 
  WDT_CTRL_RESET    =  6, 
  WDT_CTRL_FORCE    =  7, 
  WDT_CTRL_LOCK     =  8, 
  WDT_CTRL_DBEN     =  9, 
  WDT_CTRL_HALF     = 10, 
  WDT_CTRL_PAUSE    = 11, 
  WDT_CTRL_PWD_LSB  = 16, 
  WDT_CTRL_PWD_MSB  = 31  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  const uint32_t INPUT_LO;  
  const uint32_t INPUT_HI;  
  uint32_t       OUTPUT_LO; 
  uint32_t       OUTPUT_HI; 
} neorv32_gpio_t;
 
#define NEORV32_GPIO_BASE (0xFFFFFFC0UL)
 
#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (NEORV32_GPIO_BASE)))
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL; 
  uint32_t DATA; 
} neorv32_neoled_t;
 
#define NEORV32_NEOLED_BASE (0xFFFFFFD8UL)
 
#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (NEORV32_NEOLED_BASE)))
 
enum NEORV32_NEOLED_CTRL_enum {
  NEOLED_CTRL_EN         =  0, 
  NEOLED_CTRL_MODE       =  1, 
  NEOLED_CTRL_STROBE     =  2, 
  NEOLED_CTRL_PRSC0      =  3, 
  NEOLED_CTRL_PRSC1      =  4, 
  NEOLED_CTRL_PRSC2      =  5, 
  //
  NEOLED_CTRL_BUFS_0     =  6, 
  NEOLED_CTRL_BUFS_1     =  7, 
  NEOLED_CTRL_BUFS_2     =  8, 
  NEOLED_CTRL_BUFS_3     =  9, 
  //
  NEOLED_CTRL_T_TOT_0    = 10, 
  NEOLED_CTRL_T_TOT_1    = 11, 
  NEOLED_CTRL_T_TOT_2    = 12, 
  NEOLED_CTRL_T_TOT_3    = 13, 
  NEOLED_CTRL_T_TOT_4    = 14, 
  //
  NEOLED_CTRL_T_ZERO_H_0 = 15, 
  NEOLED_CTRL_T_ZERO_H_1 = 16, 
  NEOLED_CTRL_T_ZERO_H_2 = 17, 
  NEOLED_CTRL_T_ZERO_H_3 = 18, 
  NEOLED_CTRL_T_ZERO_H_4 = 19, 
  //
  NEOLED_CTRL_T_ONE_H_0  = 20, 
  NEOLED_CTRL_T_ONE_H_1  = 21, 
  NEOLED_CTRL_T_ONE_H_2  = 22, 
  NEOLED_CTRL_T_ONE_H_3  = 23, 
  NEOLED_CTRL_T_ONE_H_4  = 24, 
  //
  NEOLED_CTRL_IRQ_CONF   = 27, 
  NEOLED_CTRL_TX_EMPTY   = 28, 
  NEOLED_CTRL_TX_HALF    = 29, 
  NEOLED_CTRL_TX_FULL    = 30, 
  NEOLED_CTRL_TX_BUSY    = 31  
};
/**********************************************************************/
typedef struct __attribute__((packed,aligned(4))) {
  const uint32_t CLK;         
  const uint32_t reserved;    
  const uint32_t SOC;         
  const uint32_t CACHE;       
  const uint32_t ISPACE_BASE; 
  const uint32_t DSPACE_BASE; 
  const uint32_t IMEM_SIZE;   
  const uint32_t DMEM_SIZE;   
} neorv32_sysinfo_t;
 
#define NEORV32_SYSINFO_BASE (0xFFFFFFE0UL)
 
#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE)))
 
enum NEORV32_SYSINFO_SOC_enum {
  SYSINFO_SOC_BOOTLOADER     =  0, 
  SYSINFO_SOC_MEM_EXT        =  1, 
  SYSINFO_SOC_MEM_INT_IMEM   =  2, 
  SYSINFO_SOC_MEM_INT_DMEM   =  3, 
  SYSINFO_SOC_MEM_EXT_ENDIAN =  4, 
  SYSINFO_SOC_ICACHE         =  5, 
  SYSINFO_SOC_IS_SIM         = 13, 
  SYSINFO_SOC_OCD            = 14, 
  SYSINFO_SOC_HW_RESET       = 15, 
  SYSINFO_SOC_IO_GPIO        = 16, 
  SYSINFO_SOC_IO_MTIME       = 17, 
  SYSINFO_SOC_IO_UART0       = 18, 
  SYSINFO_SOC_IO_SPI         = 19, 
  SYSINFO_SOC_IO_TWI         = 20, 
  SYSINFO_SOC_IO_PWM         = 21, 
  SYSINFO_SOC_IO_WDT         = 22, 
  SYSINFO_SOC_IO_CFS         = 23, 
  SYSINFO_SOC_IO_TRNG        = 24, 
  SYSINFO_SOC_IO_SLINK       = 25, 
  SYSINFO_SOC_IO_UART1       = 26, 
  SYSINFO_SOC_IO_NEOLED      = 27, 
  SYSINFO_SOC_IO_XIRQ        = 28, 
  SYSINFO_SOC_IO_GPTMR       = 29, 
  SYSINFO_SOC_IO_XIP         = 30  
};
 
 enum NEORV32_SYSINFO_CACHE_enum {
  SYSINFO_CACHE_IC_BLOCK_SIZE_0    =  0, 
  SYSINFO_CACHE_IC_BLOCK_SIZE_1    =  1, 
  SYSINFO_CACHE_IC_BLOCK_SIZE_2    =  2, 
  SYSINFO_CACHE_IC_BLOCK_SIZE_3    =  3, 
  SYSINFO_CACHE_IC_NUM_BLOCKS_0    =  4, 
  SYSINFO_CACHE_IC_NUM_BLOCKS_1    =  5, 
  SYSINFO_CACHE_IC_NUM_BLOCKS_2    =  6, 
  SYSINFO_CACHE_IC_NUM_BLOCKS_3    =  7, 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_0 =  8, 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_1 =  9, 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_2 = 10, 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_3 = 11, 
  SYSINFO_CACHE_IC_REPLACEMENT_0   = 12, 
  SYSINFO_CACHE_IC_REPLACEMENT_1   = 13, 
  SYSINFO_CACHE_IC_REPLACEMENT_2   = 14, 
  SYSINFO_CACHE_IC_REPLACEMENT_3   = 15, 
};
// ----------------------------------------------------------------------------
// Include all system header files
// ----------------------------------------------------------------------------
// intrinsics
#include "neorv32_intrinsics.h"
 
// cpu core
#include "neorv32_cpu.h"
#include "neorv32_cpu_cfu.h"
 
// neorv32 runtime environment
#include "neorv32_rte.h"
 
// io/peripheral devices
#include "neorv32_cfs.h"
#include "neorv32_gpio.h"
#include "neorv32_gptmr.h"
#include "neorv32_mtime.h"
#include "neorv32_neoled.h"
#include "neorv32_pwm.h"
#include "neorv32_slink.h"
#include "neorv32_spi.h"
#include "neorv32_trng.h"
#include "neorv32_twi.h"
#include "neorv32_uart.h"
#include "neorv32_wdt.h"
#include "neorv32_xip.h"
#include "neorv32_xirq.h"
 
#ifdef __cplusplus
}
#endif
 
#endif // neorv32_h