31#define IO_BASE_ADDRESS (0XFFE00000U)
32#define NEORV32_BOOTROM_BASE (0xFFE00000U)
42#define NEORV32_TWD_BASE (0xFFEA0000U)
43#define NEORV32_CFS_BASE (0xFFEB0000U)
44#define NEORV32_SLINK_BASE (0xFFEC0000U)
45#define NEORV32_DMA_BASE (0xFFED0000U)
46#define NEORV32_CRC_BASE (0xFFEE0000U)
48#define NEORV32_PWM_BASE (0xFFF00000U)
49#define NEORV32_GPTMR_BASE (0xFFF10000U)
50#define NEORV32_ONEWIRE_BASE (0xFFF20000U)
52#define NEORV32_CLINT_BASE (0xFFF40000U)
53#define NEORV32_UART0_BASE (0xFFF50000U)
54#define NEORV32_UART1_BASE (0xFFF60000U)
55#define NEORV32_SDI_BASE (0xFFF70000U)
56#define NEORV32_SPI_BASE (0xFFF80000U)
57#define NEORV32_TWI_BASE (0xFFF90000U)
58#define NEORV32_TRNG_BASE (0xFFFA0000U)
59#define NEORV32_WDT_BASE (0xFFFB0000U)
60#define NEORV32_GPIO_BASE (0xFFFC0000U)
61#define NEORV32_NEOLED_BASE (0xFFFD0000U)
62#define NEORV32_SYSINFO_BASE (0xFFFE0000U)
63#define NEORV32_DM_BASE (0xFFFF0000U)
73#define TWD_FIRQ_ENABLE CSR_MIE_FIRQ0E
74#define TWD_FIRQ_PENDING CSR_MIP_FIRQ0P
75#define TWD_RTE_ID RTE_TRAP_FIRQ_0
76#define TWD_TRAP_CODE TRAP_CODE_FIRQ_0
80#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E
81#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P
82#define CFS_RTE_ID RTE_TRAP_FIRQ_1
83#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1
87#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E
88#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P
89#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2
90#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2
91#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E
92#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P
93#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3
94#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_3
98#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E
99#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P
100#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4
101#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4
102#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E
103#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P
104#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5
105#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5
109#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E
110#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P
111#define SPI_RTE_ID RTE_TRAP_FIRQ_6
112#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6
116#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E
117#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P
118#define TWI_RTE_ID RTE_TRAP_FIRQ_7
119#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7
123#define GPIO_FIRQ_ENABLE CSR_MIE_FIRQ8E
124#define GPIO_FIRQ_PENDING CSR_MIP_FIRQ8P
125#define GPIO_RTE_ID RTE_TRAP_FIRQ_8
126#define GPIO_TRAP_CODE TRAP_CODE_FIRQ_8
130#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E
131#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P
132#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9
133#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9
137#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E
138#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P
139#define DMA_RTE_ID RTE_TRAP_FIRQ_10
140#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10
144#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E
145#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P
146#define SDI_RTE_ID RTE_TRAP_FIRQ_11
147#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11
151#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E
152#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P
153#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12
154#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12
158#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E
159#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P
160#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13
161#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13
165#define SLINK_RX_FIRQ_ENABLE CSR_MIE_FIRQ14E
166#define SLINK_RX_FIRQ_PENDING CSR_MIP_FIRQ14P
167#define SLINK_RX_RTE_ID RTE_TRAP_FIRQ_14
168#define SLINK_RX_TRAP_CODE TRAP_CODE_FIRQ_14
169#define SLINK_TX_FIRQ_ENABLE CSR_MIE_FIRQ15E
170#define SLINK_TX_FIRQ_PENDING CSR_MIP_FIRQ15P
171#define SLINK_TX_RTE_ID RTE_TRAP_FIRQ_15
172#define SLINK_TX_TRAP_CODE TRAP_CODE_FIRQ_15
185#define neorv32_heap_begin_c ((uint32_t)&__heap_start[0])
186#define neorv32_heap_end_c ((uint32_t)&__heap_end[0])
187#define neorv32_heap_size_c ((uint32_t)&__crt0_max_heap[0])
215 uint32_t uint32[
sizeof(uint64_t)/
sizeof(uint32_t)];
216 uint16_t uint16[
sizeof(uint64_t)/
sizeof(uint16_t)];
217 uint8_t uint8[
sizeof(uint64_t)/
sizeof(uint8_t)];
221 uint32_t uint32[
sizeof(uint32_t)/
sizeof(uint32_t)];
222 uint16_t uint16[
sizeof(uint32_t)/
sizeof(uint16_t)];
223 uint8_t uint8[
sizeof(uint32_t)/
sizeof(uint8_t)];
227 uint16_t uint16[
sizeof(uint16_t)/
sizeof(uint16_t)];
228 uint8_t uint8[
sizeof(uint16_t)/
sizeof(uint8_t)];
NEORV32_CLOCK_PRSC_enum
Definition neorv32.h:195
@ CLK_PRSC_4096
Definition neorv32.h:203
@ CLK_PRSC_1024
Definition neorv32.h:201
@ CLK_PRSC_64
Definition neorv32.h:199
@ CLK_PRSC_4
Definition neorv32.h:197
@ CLK_PRSC_128
Definition neorv32.h:200
@ CLK_PRSC_2048
Definition neorv32.h:202
@ CLK_PRSC_8
Definition neorv32.h:198
@ CLK_PRSC_2
Definition neorv32.h:196
General auxiliary functions header file.
Custom Functions Subsystem (CFS) HW driver header file.
Hardware Local Interruptor (CLINT) HW driver header file.
CPU Core Functions HW driver header file.
CPU Core custom functions unit HW driver header file.
Control and Status Registers (CSR) definitions.
Cyclic redundancy check unit (CRC) HW driver header file.
Direct Memory Access Controller (DMA) HW driver header file.
General purpose input/output port unit (GPIO) HW driver header file.
General purpose timer (GPTMR) HW driver header file.
Helper macros for custom "intrinsics" / instructions.
Smart LED Interface (NEOLED) HW driver header file.
1-Wire Interface Controller (ONEWIRE) HW driver header file.
Pulse-Width Modulation Controller (PWM) HW driver header file.
NEORV32 Runtime Environment.
Serial data interface controller (SPPI) HW driver header file.
Stream Link Interface HW driver header file.
Symmetric multiprocessing (SMP) library header file.
Serial peripheral interface controller (SPI) HW driver header file.
System Information Memory (SYSINFO) HW driver header file.
True Random Number Generator (TRNG) HW driver header file.
Two-Wire Device Controller (TWD) HW driver header file.
Two-Wire Interface Controller (TWI) HW driver header file.
Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file.
Watchdog Timer (WDT) HW driver header file.