NEORV32 - Software Framework Documentation
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neorv32.h
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1// ================================================================================ //
2// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
3// Copyright (c) NEORV32 contributors. //
4// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //
5// Licensed under the BSD-3-Clause license, see LICENSE for details. //
6// SPDX-License-Identifier: BSD-3-Clause //
7// ================================================================================ //
8
16#ifndef neorv32_h
17#define neorv32_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23// Standard libraries
24#include <stdint.h>
25#include <inttypes.h>
26#include <limits.h>
27#include <unistd.h>
28#include <stdlib.h>
29
30
31/**********************************************************************/
44
45
46/**********************************************************************/
52#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E
53#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P
54#define CFS_RTE_ID RTE_TRAP_FIRQ_1
55#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1
59#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E
60#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P
61#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2
62#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2
63#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E
64#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P
65#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3
66#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_3
70#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E
71#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P
72#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4
73#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4
74#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E
75#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P
76#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5
77#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5
81#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E
82#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P
83#define SPI_RTE_ID RTE_TRAP_FIRQ_6
84#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6
88#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E
89#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P
90#define TWI_RTE_ID RTE_TRAP_FIRQ_7
91#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7
95#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E
96#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P
97#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8
98#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8
102#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E
103#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P
104#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9
105#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9
109#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E
110#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P
111#define DMA_RTE_ID RTE_TRAP_FIRQ_10
112#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10
116#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E
117#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P
118#define SDI_RTE_ID RTE_TRAP_FIRQ_11
119#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11
123#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E
124#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P
125#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12
126#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12
130#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E
131#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P
132#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13
133#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13
137#define SLINK_RX_FIRQ_ENABLE CSR_MIE_FIRQ14E
138#define SLINK_RX_FIRQ_PENDING CSR_MIP_FIRQ14P
139#define SLINK_RX_RTE_ID RTE_TRAP_FIRQ_14
140#define SLINK_RX_TRAP_CODE TRAP_CODE_FIRQ_14
141#define SLINK_TX_FIRQ_ENABLE CSR_MIE_FIRQ15E
142#define SLINK_TX_FIRQ_PENDING CSR_MIP_FIRQ15P
143#define SLINK_TX_RTE_ID RTE_TRAP_FIRQ_15
144#define SLINK_TX_TRAP_CODE TRAP_CODE_FIRQ_15
149/**********************************************************************/
154#define XIP_MEM_BASE_ADDRESS (0xE0000000U)
156#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U)
158#define IO_BASE_ADDRESS (0xFFFFE000U)
162/**********************************************************************/
166#define NEORV32_CFS_BASE (0xFFFFEB00U)
167#define NEORV32_SLINK_BASE (0xFFFFEC00U)
168#define NEORV32_DMA_BASE (0xFFFFED00U)
169#define NEORV32_CRC_BASE (0xFFFFEE00U)
170#define NEORV32_XIP_BASE (0xFFFFEF00U)
171#define NEORV32_PWM_BASE (0xFFFFF000U)
172#define NEORV32_GPTMR_BASE (0xFFFFF100U)
173#define NEORV32_ONEWIRE_BASE (0xFFFFF200U)
174#define NEORV32_XIRQ_BASE (0xFFFFF300U)
175#define NEORV32_MTIME_BASE (0xFFFFF400U)
176#define NEORV32_UART0_BASE (0xFFFFF500U)
177#define NEORV32_UART1_BASE (0xFFFFF600U)
178#define NEORV32_SDI_BASE (0xFFFFF700U)
179#define NEORV32_SPI_BASE (0xFFFFF800U)
180#define NEORV32_TWI_BASE (0xFFFFF900U)
181#define NEORV32_TRNG_BASE (0xFFFFFA00U)
182#define NEORV32_WDT_BASE (0xFFFFFB00U)
183#define NEORV32_GPIO_BASE (0xFFFFFC00U)
184#define NEORV32_NEOLED_BASE (0xFFFFFD00U)
185#define NEORV32_SYSINFO_BASE (0xFFFFFE00U)
186#define NEORV32_DM_BASE (0xFFFFFF00U)
190// ----------------------------------------------------------------------------
191// Include all system header files
192// ----------------------------------------------------------------------------
193// intrinsics
194#include "neorv32_intrinsics.h"
195
196// cpu core
197#include "neorv32_cpu.h"
198#include "neorv32_cpu_amo.h"
199#include "neorv32_cpu_csr.h"
200#include "neorv32_cpu_cfu.h"
201
202// NEORV32 runtime environment
203#include "neorv32_rte.h"
204
205// IO/peripheral devices
206#include "neorv32_cfs.h"
207#include "neorv32_crc.h"
208#include "neorv32_dm.h"
209#include "neorv32_dma.h"
210#include "neorv32_gpio.h"
211#include "neorv32_gptmr.h"
212#include "neorv32_mtime.h"
213#include "neorv32_neoled.h"
214#include "neorv32_onewire.h"
215#include "neorv32_pwm.h"
216#include "neorv32_sdi.h"
217#include "neorv32_slink.h"
218#include "neorv32_spi.h"
219#include "neorv32_sysinfo.h"
220#include "neorv32_trng.h"
221#include "neorv32_twi.h"
222#include "neorv32_uart.h"
223#include "neorv32_wdt.h"
224#include "neorv32_xip.h"
225#include "neorv32_xirq.h"
226
227#ifdef __cplusplus
228}
229#endif
230
231#endif // neorv32_h
NEORV32_CLOCK_PRSC_enum
Definition neorv32.h:34
@ CLK_PRSC_4096
Definition neorv32.h:42
@ CLK_PRSC_1024
Definition neorv32.h:40
@ CLK_PRSC_64
Definition neorv32.h:38
@ CLK_PRSC_4
Definition neorv32.h:36
@ CLK_PRSC_128
Definition neorv32.h:39
@ CLK_PRSC_2048
Definition neorv32.h:41
@ CLK_PRSC_8
Definition neorv32.h:37
@ CLK_PRSC_2
Definition neorv32.h:35
Custom Functions Subsystem (CFS) HW driver header file.
CPU Core Functions HW driver header file.
Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - header file.
CPU Core custom functions unit HW driver header file.
Control and Status Registers (CSR) definitions.
Cyclic redundancy check unit (CRC) HW driver header file.
On-Chip Debugger "debug-module" HW driver header file.
Direct Memory Access Controller (DMA) HW driver header file.
General purpose input/output port unit (GPIO) HW driver header file.
General purpose timer (GPTMR) HW driver header file.
Helper functions and macros for custom "intrinsics" / instructions.
Machine System Timer (MTIME) HW driver header file.
Smart LED Interface (NEOLED) HW driver header file.
1-Wire Interface Controller (ONEWIRE) HW driver header file.
Pulse-Width Modulation Controller (PWM) HW driver header file.
NEORV32 Runtime Environment.
Serial data interface controller (SPPI) HW driver header file.
Serial peripheral interface controller (SPI) HW driver header file.
True Random Number Generator (TRNG) HW driver header file.
Two-Wire Interface Controller (TWI) HW driver header file.
Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file.
Watchdog Timer (WDT) HW driver header file.
Execute in place module (XIP) HW driver header file.
External Interrupt controller HW driver header file.