NEORV32 Software Framework Documentation
The NEORV32 RISC-V Processor
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neorv32_xip.h File Reference

Execute in place module (XIP) HW driver header file. More...

#include <stdint.h>

Go to the source code of this file.

Data Structures

struct  neorv32_xip_t
 

Functions

Prototypes
int neorv32_xip_available (void)
 
void neorv32_xip_setup (int prsc, int cdiv, int cpol, int cpha, uint8_t rd_cmd)
 
int neorv32_xip_start (int abytes)
 
void neorv32_xip_highspeed_enable (void)
 
void neorv32_xip_highspeed_disable (void)
 
uint32_t neorv32_xip_get_clock_speed (void)
 
void neorv32_xip_spi_trans (int nbytes, uint64_t *rtx_data)
 

IO Device: Execute In Place Module (XIP)

#define NEORV32_XIP   ((neorv32_xip_t*) (NEORV32_XIP_BASE))
 
enum  NEORV32_XIP_CTRL_enum {
  XIP_CTRL_EN = 0 , XIP_CTRL_PRSC0 = 1 , XIP_CTRL_PRSC1 = 2 , XIP_CTRL_PRSC2 = 3 ,
  XIP_CTRL_CPOL = 4 , XIP_CTRL_CPHA = 5 , XIP_CTRL_SPI_NBYTES_LSB = 6 , XIP_CTRL_SPI_NBYTES_MSB = 9 ,
  XIP_CTRL_XIP_EN = 10 , XIP_CTRL_XIP_ABYTES_LSB = 11 , XIP_CTRL_XIP_ABYTES_MSB = 12 , XIP_CTRL_RD_CMD_LSB = 13 ,
  XIP_CTRL_RD_CMD_MSB = 20 , XIP_CTRL_SPI_CSEN = 21 , XIP_CTRL_HIGHSPEED = 22 , XIP_CTRL_CDIV0 = 23 ,
  XIP_CTRL_CDIV1 = 24 , XIP_CTRL_CDIV2 = 25 , XIP_CTRL_CDIV3 = 26 , XIP_CTRL_BURST_EN = 29 ,
  XIP_CTRL_PHY_BUSY = 30 , XIP_CTRL_XIP_BUSY = 31
}
 

Detailed Description

Execute in place module (XIP) HW driver header file.

Note
These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).
See also
https://stnolting.github.io/neorv32/sw/files.html

Macro Definition Documentation

◆ NEORV32_XIP

#define NEORV32_XIP   ((neorv32_xip_t*) (NEORV32_XIP_BASE))

XIP module hardware access (neorv32_xip_t)

Enumeration Type Documentation

◆ NEORV32_XIP_CTRL_enum

XIP control/data register bits

Enumerator
XIP_CTRL_EN 

XIP control register( 0) (r/w): XIP module enable

XIP_CTRL_PRSC0 

XIP control register( 1) (r/w): Clock prescaler select bit 0

XIP_CTRL_PRSC1 

XIP control register( 2) (r/w): Clock prescaler select bit 1

XIP_CTRL_PRSC2 

XIP control register( 3) (r/w): Clock prescaler select bit 2

XIP_CTRL_CPOL 

XIP control register( 4) (r/w): SPI (idle) clock polarity

XIP_CTRL_CPHA 

XIP control register( 5) (r/w): SPI clock phase

XIP_CTRL_SPI_NBYTES_LSB 

XIP control register( 6) (r/w): Number of bytes in SPI transmission, LSB

XIP_CTRL_SPI_NBYTES_MSB 

XIP control register( 9) (r/w): Number of bytes in SPI transmission, MSB

XIP_CTRL_XIP_EN 

XIP control register(10) (r/w): XIP access enable

XIP_CTRL_XIP_ABYTES_LSB 

XIP control register(11) (r/w): Number XIP address bytes (minus 1), LSB

XIP_CTRL_XIP_ABYTES_MSB 

XIP control register(12) (r/w): Number XIP address bytes (minus 1), MSB

XIP_CTRL_RD_CMD_LSB 

XIP control register(13) (r/w): SPI flash read command, LSB

XIP_CTRL_RD_CMD_MSB 

XIP control register(20) (r/w): SPI flash read command, MSB

XIP_CTRL_SPI_CSEN 

XIP control register(21) (r/w): SPI chip-select enable

XIP_CTRL_HIGHSPEED 

XIP control register(22) (r/w): SPI high-speed mode enable (ignoring XIP_CTRL_PRSC)

XIP_CTRL_CDIV0 

XIP control register(23) (r/w): Clock divider bit 0

XIP_CTRL_CDIV1 

XIP control register(24) (r/w): Clock divider bit 1

XIP_CTRL_CDIV2 

XIP control register(25) (r/w): Clock divider bit 2

XIP_CTRL_CDIV3 

XIP control register(26) (r/w): Clock divider bit 3

XIP_CTRL_BURST_EN 

XIP control register(29) (r/-): Burst mode enabled (set if XIP cache is implemented)

XIP_CTRL_PHY_BUSY 

XIP control register(30) (r/-): SPI PHY is busy

XIP_CTRL_XIP_BUSY 

XIP control register(31) (r/-): XIP access in progress

Function Documentation

◆ neorv32_xip_available()

int neorv32_xip_available ( void )

Check if XIP module was synthesized.

Returns
0 if XIP was not synthesized, 1 if XIP is available.

◆ neorv32_xip_get_clock_speed()

uint32_t neorv32_xip_get_clock_speed ( void )

Get configured clock speed in Hz.

Returns
Actual configured XIP clock speed in Hz.

◆ neorv32_xip_highspeed_disable()

void neorv32_xip_highspeed_disable ( void )

Disable high-speed SPI mode.

◆ neorv32_xip_highspeed_enable()

void neorv32_xip_highspeed_enable ( void )

Enable high-speed SPI mode (running at half of the processor clock).

Note
High-speed SPI mode ignores the programmed clock prescaler configuration.

◆ neorv32_xip_setup()

void neorv32_xip_setup ( int prsc,
int cdiv,
int cpol,
int cpha,
uint8_t rd_cmd )

Configure XIP module: configure SPI/flash properties.

Warning
This will reset the XIP module overriding the CTRL register.
Note
This function will also send 64 dummy clocks via the SPI port (with chip-select disabled).
Parameters
[in]prscSPI clock prescaler select (0..7). @prama[in] cdiv Clock divider (0..15).
[in]cpolSPI clock polarity (0/1).
[in]cphaSPI clock phase(0/1).
[in]rd_cmdSPI flash read byte command.

◆ neorv32_xip_spi_trans()

void neorv32_xip_spi_trans ( int nbytes,
uint64_t * rtx_data )

Direct SPI access to the XIP flash.

Warning
This function can only be used BEFORE the XIP-mode is activated!
Note
This function is blocking.
Parameters
[in]nbytesNumber of bytes to transfer (1..8).
[in,out]rtx_dataPointer to 64-bit TX/RX data (MSB-aligned for sending, LSB-aligned for receiving (only 32-bit)).
Returns
0 if valid transfer, 1 if transfer configuration error.

◆ neorv32_xip_start()

int neorv32_xip_start ( int abytes)

Enable XIP mode (to allow CPU to transparently fetch data & instructions).

Parameters
[in]abytesNumber of address bytes used to access the SPI flash (1,2,3,4).
Returns
0 if XIP configuration is OK, -1 if configuration error.