neorv32_smc.h

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// ================================================================================ //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
// Copyright (c) NEORV32 contributors.                                              //
// Copyright (c) 2020 - 2026 Stephan Nolting. All rights reserved.                  //
// Licensed under the BSD-3-Clause license, see LICENSE for details.                //
// SPDX-License-Identifier: BSD-3-Clause                                            //
// ================================================================================ //
 
#ifndef NEORV32_SMC_H
#define NEORV32_SMC_H
 
#include <neorv32.h>
#include <stdint.h>
 
/**********************************************************************/
typedef volatile struct __attribute__((packed,aligned(4))) {
  uint32_t CSR0; 
  uint32_t CSR1; 
} neorv32_smc_t;
 
#define NEORV32_SMC ((neorv32_smc_t*) (NEORV32_SMC_BASE))
 
enum NEORV32_SMC_CFG0_enum {
  SMC_CSR0_EN        =  0, 
  SMC_CSR0_IOEN      =  1, 
  SMC_CSR0_DUAL      =  3, 
  SMC_CSR0_BUSY      =  4, 
  SMC_CSR0_MSIZE_LSB =  7, 
  SMC_CSR0_MSIZE_MSB =  8, 
  SMC_CSR0_CDIV_LSB  =  9, 
  SMC_CSR0_CDIV_MSB  = 11, 
  SMC_CSR0_RWAIT_LSB = 12, 
  SMC_CSR0_RWAIT_MSB = 15, 
  SMC_CSR0_RCMD_LSB  = 16, 
  SMC_CSR0_RCMD_MSB  = 23, 
  SMC_CSR0_WCMD_LSB  = 24, 
  SMC_CSR0_WCMD_MSB  = 31  
};
 
enum NEORV32_SMC_CFG1_enum {
  SMC_CSR1_ICMD0_LSB    =  0, 
  SMC_CSR1_ICMD0_MSB    =  7, 
  SMC_CSR1_ICMD1_LSB    =  8, 
  SMC_CSR1_ICMD1_MSB    = 15, 
  SMC_CSR1_ICMD2_LSB    = 16, 
  SMC_CSR1_ICMD2_MSB    = 23, 
  SMC_CSR1_MEM_BASE_LSB = 28, 
  SMC_CSR1_MEM_BASE_MSB = 31  
};
/**********************************************************************/
enum NEORV32_SMC_MSIZE_enum {
  SMC_MSIZE_2MB  = 0b00, 
  SMC_MSIZE_4MB  = 0b01, 
  SMC_MSIZE_8MB  = 0b10, 
  SMC_MSIZE_16MB = 0b11  
};
/**********************************************************************/
int      neorv32_smc_available(void);
void     neorv32_smc_setup(int dual, int msize, int cdiv, int rwait, uint8_t rcmd, uint8_t wcmd, uint32_t icmd);
int      neorv32_smc_busy(void);
void     neorv32_smc_pins_enable(void);
void     neorv32_smc_pins_disable(void);
uint32_t neorv32_smc_get_clockspeed(void);
uint32_t neorv32_smc_get_baseaddr(void);
#endif // NEORV32_SMC_H