neorv32_smc.h File Reference

Serial memory controller (SMC) HW driver header file. More...

#include <neorv32.h>
#include <stdint.h>

Go to the source code of this file.

Data Structures
struct	neorv32_smc_t

Enumerations
enum	NEORV32_SMC_MSIZE_enum { SMC_MSIZE_2MB = 0b00 , SMC_MSIZE_4MB = 0b01 , SMC_MSIZE_8MB = 0b10 , SMC_MSIZE_16MB = 0b11 }

Functions
Prototypes
int	neorv32_smc_available (void)
void	neorv32_smc_setup (int dual, int msize, int cdiv, int rwait, uint8_t rcmd, uint8_t wcmd, uint32_t icmd)
int	neorv32_smc_busy (void)
void	neorv32_smc_pins_enable (void)
void	neorv32_smc_pins_disable (void)
uint32_t	neorv32_smc_get_clockspeed (void)
uint32_t	neorv32_smc_get_baseaddr (void)

IO Device: Serial Memory Controller (SMC)
#define	NEORV32_SMC   ((neorv32_smc_t*) (NEORV32_SMC_BASE))
enum	NEORV32_SMC_CFG0_enum {   SMC_CSR0_EN = 0 , SMC_CSR0_IOEN = 1 , SMC_CSR0_DUAL = 3 , SMC_CSR0_BUSY = 4 ,   SMC_CSR0_MSIZE_LSB = 7 , SMC_CSR0_MSIZE_MSB = 8 , SMC_CSR0_CDIV_LSB = 9 , SMC_CSR0_CDIV_MSB = 11 ,   SMC_CSR0_RWAIT_LSB = 12 , SMC_CSR0_RWAIT_MSB = 15 , SMC_CSR0_RCMD_LSB = 16 , SMC_CSR0_RCMD_MSB = 23 ,   SMC_CSR0_WCMD_LSB = 24 , SMC_CSR0_WCMD_MSB = 31 }
enum	NEORV32_SMC_CFG1_enum {   SMC_CSR1_ICMD0_LSB = 0 , SMC_CSR1_ICMD0_MSB = 7 , SMC_CSR1_ICMD1_LSB = 8 , SMC_CSR1_ICMD1_MSB = 15 ,   SMC_CSR1_ICMD2_LSB = 16 , SMC_CSR1_ICMD2_MSB = 23 , SMC_CSR1_MEM_BASE_LSB = 28 , SMC_CSR1_MEM_BASE_MSB = 31 }

Detailed Description

Serial memory controller (SMC) HW driver header file.

Macro Definition Documentation

NEORV32_SMC

#define NEORV32_SMC   ((neorv32_smc_t*) (NEORV32_SMC_BASE))

SMC hardware handle (neorv32_smc_t)

Enumeration Type Documentation

NEORV32_SMC_CFG0_enum

enum NEORV32_SMC_CFG0_enum

SMC control and status register 0 (CSR0) bits

Enumerator
SMC_CSR0_EN	SMC CSR0 (0) (r/w): SMC global enable
SMC_CSR0_IOEN	SMC CSR0 (1) (r/w): Enable control of SMC IO pins
SMC_CSR0_DUAL	SMC CSR0 (3) (r/w): Enable dual-chip mode
SMC_CSR0_BUSY	SMC CSR0 (4) (r/-): Memory operation in progress when set
SMC_CSR0_MSIZE_LSB	SMC CSR0 (7) (r/w): Memory size select, LSB
SMC_CSR0_MSIZE_MSB	SMC CSR0 (8) (r/w): Memory size select, MSB
SMC_CSR0_CDIV_LSB	SMC CSR0 (9) (r/w): SPI clock divider, LSB
SMC_CSR0_CDIV_MSB	SMC CSR0 (11) (r/w): SPI clock divider, MSB
SMC_CSR0_RWAIT_LSB	SMC CSR0 (12) (r/w): Read access dummy/wait cycles, LSB
SMC_CSR0_RWAIT_MSB	SMC CSR0 (15) (r/w): Read access dummy/wait cycles, MSB
SMC_CSR0_RCMD_LSB	SMC CSR0 (16) (r/w): Read command, LSB
SMC_CSR0_RCMD_MSB	SMC CSR0 (23) (r/w): Read command, MSB
SMC_CSR0_WCMD_LSB	SMC CSR0 (24) (r/w): Write command, LSB
SMC_CSR0_WCMD_MSB	SMC CSR0 (31) (r/w): Write command, MSB

NEORV32_SMC_CFG1_enum

enum NEORV32_SMC_CFG1_enum

SMC control and status register 1 (CSR1) bits

Enumerator
SMC_CSR1_ICMD0_LSB	SMC CSR1 (0) (r/w): Memory initialization command 0, LSB
SMC_CSR1_ICMD0_MSB	SMC CSR1 (7) (r/w): Memory initialization command 0, MSB
SMC_CSR1_ICMD1_LSB	SMC CSR1 (8) (r/w): Memory initialization command 1, LSB
SMC_CSR1_ICMD1_MSB	SMC CSR1 (15) (r/w): Memory initialization command 1, MSB
SMC_CSR1_ICMD2_LSB	SMC CSR1 (16) (r/w): Memory initialization command 2, LSB
SMC_CSR1_ICMD2_MSB	SMC CSR1 (23) (r/w): Memory initialization command 2, MSB
SMC_CSR1_MEM_BASE_LSB	SMC CSR1 (28) (r/-): Memory base address (top 4 bits / 256MB page), LSB
SMC_CSR1_MEM_BASE_MSB	SMC CSR1 (31) (r/-): Memory base address (top 4 bits / 256MB page), MSB

NEORV32_SMC_MSIZE_enum

enum NEORV32_SMC_MSIZE_enum

SMC memory size select (per chip)

Enumerator
SMC_MSIZE_2MB	2 MB
SMC_MSIZE_4MB	4 MB
SMC_MSIZE_8MB	8 MB
SMC_MSIZE_16MB	16 MB

Function Documentation

neorv32_smc_available()

int neorv32_smc_available

(

void

)

Check if SMC was synthesized.

Returns

0 if SMC was not synthesized, non-zero if SMC is available.

neorv32_smc_busy()

int neorv32_smc_busy

(

void

)

Check if a SMC memory operation is in progress.

Returns

Zero if SMC is idle, non-zero if memory operation in progress.

neorv32_smc_get_baseaddr()

uint32_t neorv32_smc_get_baseaddr

(

void

)

Get configured SMC memory base address.

Returns

Configured base address for transparent memory access.

neorv32_smc_get_clockspeed()

uint32_t neorv32_smc_get_clockspeed

(

void

)

Get configured SMC SPI clock speed in Hz.

Returns

Configured SMC interface clock speed in Hz.

neorv32_smc_pins_disable()

void neorv32_smc_pins_disable

(

void

)

Disable SMC control of SMC IO pins.

neorv32_smc_pins_enable()

void neorv32_smc_pins_enable

(

void

)

Enable SMC control of SMC IO pins.

neorv32_smc_setup()

void neorv32_smc_setup	(	int	dual,
		int	msize,
		int	cdiv,
		int	rwait,
		uint8_t	rcmd,
		uint8_t	wcmd,
		uint32_t	icmd )

Reset, configure and enable SMC.

Parameters

[in]	dual	Enable dual-chip mode (0,1).
[in]	msize	Memory chip size select (NEORV32_SMC_MSIZE_enum).
[in]	cdiv	Clock divider (3-bit); f_SPI = f_cpu/(2*(cdiv+1)).
[in]	rwait	Number of read access dummy/wait cycles (0..15).
[in]	rcmd	Memory chip read command (8-bit).
[in]	wcmd	Memory chip write command (8-bit).
[in]	icmd	Initialization commands (3x8-bit, LSB-aligned).