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NEORV32 Software Framework Documentation
The NEORV32 RISC-V Processor
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Serial peripheral interface controller (SPI) HW driver header file. More...
#include <stdint.h>
Go to the source code of this file.
Data Structures | |
struct | neorv32_spi_t |
Functions | |
Prototypes | |
int | neorv32_spi_available (void) |
void | neorv32_spi_setup (int prsc, int cdiv, int clk_phase, int clk_polarity) |
uint32_t | neorv32_spi_get_clock_speed (void) |
void | neorv32_spi_disable (void) |
void | neorv32_spi_enable (void) |
int | neorv32_spi_get_fifo_depth (void) |
void | neorv32_spi_cs_en (int cs) |
void | neorv32_spi_cs_dis (void) |
uint8_t | neorv32_spi_transfer (uint8_t tx_data) |
void | neorv32_spi_put_nonblocking (uint8_t tx_data) |
uint8_t | neorv32_spi_get_nonblocking (void) |
void | neorv32_spi_cs_en_nonblocking (int cs) |
void | neorv32_spi_cs_dis_nonblocking (void) |
int | neorv32_spi_check_cs (void) |
int | neorv32_spi_rx_avail (void) |
int | neorv32_spi_tx_empty (void) |
int | neorv32_spi_tx_full (void) |
int | neorv32_spi_busy (void) |
IO Device: Serial Peripheral Interface Controller (SPI) | |
#define | NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE)) |
enum | NEORV32_SPI_CTRL_enum { SPI_CTRL_EN = 0 , SPI_CTRL_CPHA = 1 , SPI_CTRL_CPOL = 2 , SPI_CTRL_PRSC0 = 3 , SPI_CTRL_PRSC1 = 4 , SPI_CTRL_PRSC2 = 5 , SPI_CTRL_CDIV0 = 6 , SPI_CTRL_CDIV1 = 7 , SPI_CTRL_CDIV2 = 8 , SPI_CTRL_CDIV3 = 9 , SPI_CTRL_RX_AVAIL = 16 , SPI_CTRL_TX_EMPTY = 17 , SPI_CTRL_TX_FULL = 18 , SPI_CTRL_FIFO_LSB = 24 , SPI_CTRL_FIFO_MSB = 27 , SPI_CS_ACTIVE = 30 , SPI_CTRL_BUSY = 31 } |
enum | NEORV32_SPI_DATA_enum { SPI_DATA_LSB = 0 , SPI_DATA_CSEN = 3 , SPI_DATA_MSB = 7 , SPI_DATA_CMD = 31 } |
Serial peripheral interface controller (SPI) HW driver header file.
#define NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE)) |
SPI module hardware handle (neorv32_spi_t)
SPI control register bits
int neorv32_spi_available | ( | void | ) |
Check if SPI unit was synthesized.
int neorv32_spi_busy | ( | void | ) |
Check if SPI transceiver is busy or TX FIFO not empty.
int neorv32_spi_check_cs | ( | void | ) |
Check if any chip-select line is active.
void neorv32_spi_cs_dis | ( | void | ) |
Deactivate currently active SPI chip select signal.
void neorv32_spi_cs_dis_nonblocking | ( | void | ) |
Deactivate currently active SPI chip select signal (non-blocking).
void neorv32_spi_cs_en | ( | int | cs | ) |
Activate single SPI chip select signal.
cs | Chip select line to activate (0..7). |
void neorv32_spi_cs_en_nonblocking | ( | int | cs | ) |
Activate single SPI chip select signal (non-blocking).
cs | Chip select line to activate (0..7). |
void neorv32_spi_disable | ( | void | ) |
Disable SPI controller.
void neorv32_spi_enable | ( | void | ) |
Enable SPI controller.
uint32_t neorv32_spi_get_clock_speed | ( | void | ) |
Get configured clock speed in Hz.
int neorv32_spi_get_fifo_depth | ( | void | ) |
Get SPI FIFO depth.
uint8_t neorv32_spi_get_nonblocking | ( | void | ) |
Get SPI RX data (non-blocking).
void neorv32_spi_put_nonblocking | ( | uint8_t | tx_data | ) |
Put SPI TX data (non-blocking).
tx_data | Transmit data (8-bit, LSB-aligned). |
int neorv32_spi_rx_avail | ( | void | ) |
Check if RX FIFO data is available.
void neorv32_spi_setup | ( | int | prsc, |
int | cdiv, | ||
int | clk_phase, | ||
int | clk_polarity ) |
Enable and configure SPI controller. The SPI control register bits are listed in NEORV32_SPI_CTRL_enum.
[in] | prsc | Clock prescaler select (0..7). See NEORV32_CLOCK_PRSC_enum. @prama[in] cdiv Clock divider (0..15). |
[in] | clk_phase | Clock phase (0=sample on rising edge, 1=sample on falling edge). |
[in] | clk_polarity | Clock polarity (when idle). |
uint8_t neorv32_spi_transfer | ( | uint8_t | tx_data | ) |
Perform a single SPI data transfer.
tx_data | Transmit data (8-bit, LSB-aligned). |
int neorv32_spi_tx_empty | ( | void | ) |
Check if TX FIFO is empty.
int neorv32_spi_tx_full | ( | void | ) |
Check if TX FIFO is full.