neorv32_spi.h File Reference

Serial peripheral interface controller (SPI) HW driver header file. More...

#include <stdint.h>

Go to the source code of this file.

Data Structures
struct	neorv32_spi_t

Functions
Prototypes
int	neorv32_spi_available (void)
void	neorv32_spi_setup (int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t irq_mask)
void	neorv32_spi_highspeed_enable (void)
void	neorv32_spi_highspeed_disable (void)
uint32_t	neorv32_spi_get_clock_speed (void)
void	neorv32_spi_disable (void)
void	neorv32_spi_enable (void)
int	neorv32_spi_get_fifo_depth (void)
void	neorv32_spi_cs_en (int cs)
void	neorv32_spi_cs_dis (void)
uint8_t	neorv32_spi_transfer (uint8_t tx_data)
void	neorv32_spi_put_nonblocking (uint8_t tx_data)
uint8_t	neorv32_spi_get_nonblocking (void)
void	neorv32_spi_cs_en_nonblocking (int cs)
void	neorv32_spi_cs_dis_nonblocking (void)
int	neorv32_spi_check_cs (void)
int	neorv32_spi_busy (void)

IO Device: Serial Peripheral Interface Controller (SPI)
#define	NEORV32_SPI   ((neorv32_spi_t*) (NEORV32_SPI_BASE))
enum	NEORV32_SPI_CTRL_enum {   SPI_CTRL_EN = 0 , SPI_CTRL_CPHA = 1 , SPI_CTRL_CPOL = 2 , SPI_CTRL_PRSC0 = 3 ,   SPI_CTRL_PRSC1 = 4 , SPI_CTRL_PRSC2 = 5 , SPI_CTRL_CDIV0 = 6 , SPI_CTRL_CDIV1 = 7 ,   SPI_CTRL_CDIV2 = 8 , SPI_CTRL_CDIV3 = 9 , SPI_CTRL_HIGHSPEED = 10 , SPI_CTRL_RX_AVAIL = 16 ,   SPI_CTRL_TX_EMPTY = 17 , SPI_CTRL_TX_NHALF = 18 , SPI_CTRL_TX_FULL = 19 , SPI_CTRL_IRQ_RX_AVAIL = 20 ,   SPI_CTRL_IRQ_TX_EMPTY = 21 , SPI_CTRL_IRQ_TX_HALF = 22 , SPI_CTRL_IRQ_IDLE = 23 , SPI_CTRL_FIFO_LSB = 24 ,   SPI_CTRL_FIFO_MSB = 27 , SPI_CS_ACTIVE = 30 , SPI_CTRL_BUSY = 31 }
enum	NEORV32_SPI_DATA_enum { SPI_DATA_LSB = 0 , SPI_DATA_MSB = 1 , SPI_DATA_CSEN = 3 , SPI_DATA_CMD = 31 }

Detailed Description

Serial peripheral interface controller (SPI) HW driver header file.

Macro Definition Documentation

NEORV32_SPI

#define NEORV32_SPI   ((neorv32_spi_t*) (NEORV32_SPI_BASE))

SPI module hardware handle (neorv32_spi_t)

Enumeration Type Documentation

NEORV32_SPI_CTRL_enum

enum NEORV32_SPI_CTRL_enum

SPI control register bits

Enumerator
SPI_CTRL_EN	SPI control register(0) (r/w): SPI unit enable
SPI_CTRL_CPHA	SPI control register(1) (r/w): Clock phase
SPI_CTRL_CPOL	SPI control register(2) (r/w): Clock polarity
SPI_CTRL_PRSC0	SPI control register(3) (r/w): Clock prescaler select bit 0
SPI_CTRL_PRSC1	SPI control register(4) (r/w): Clock prescaler select bit 1
SPI_CTRL_PRSC2	SPI control register(5) (r/w): Clock prescaler select bit 2
SPI_CTRL_CDIV0	SPI control register(6) (r/w): Clock divider bit 0
SPI_CTRL_CDIV1	SPI control register(7) (r/w): Clock divider bit 1
SPI_CTRL_CDIV2	SPI control register(8) (r/w): Clock divider bit 2
SPI_CTRL_CDIV3	SPI control register(9) (r/w): Clock divider bit 3
SPI_CTRL_HIGHSPEED	SPI control register(10) (r/w): High-speed mode
SPI_CTRL_RX_AVAIL	SPI control register(16) (r/-): RX FIFO data available (RX FIFO not empty)
SPI_CTRL_TX_EMPTY	SPI control register(17) (r/-): TX FIFO empty
SPI_CTRL_TX_NHALF	SPI control register(18) (r/-): TX FIFO not at least half full
SPI_CTRL_TX_FULL	SPI control register(19) (r/-): TX FIFO full
SPI_CTRL_IRQ_RX_AVAIL	SPI control register(20) (r/w): Fire IRQ if RX FIFO data available (RX FIFO not empty)
SPI_CTRL_IRQ_TX_EMPTY	SPI control register(21) (r/w): Fire IRQ if TX FIFO empty
SPI_CTRL_IRQ_TX_HALF	SPI control register(22) (r/w): Fire IRQ if TX FIFO not at least half full
SPI_CTRL_IRQ_IDLE	SPI control register(23) (r/w): Fire IRQ if TX FIFO is empty and SPI bus engine is idle
SPI_CTRL_FIFO_LSB	SPI control register(24) (r/-): log2(FIFO size), lsb
SPI_CTRL_FIFO_MSB	SPI control register(27) (r/-): log2(FIFO size), msb
SPI_CS_ACTIVE	SPI control register(30) (r/-): At least one CS line is active when set
SPI_CTRL_BUSY	SPI control register(31) (r/-): SPI busy flag

NEORV32_SPI_DATA_enum

enum NEORV32_SPI_DATA_enum

SPI data register bits

Enumerator
SPI_DATA_LSB	SPI data register(0) (r/w): Data byte LSB
SPI_DATA_MSB	SPI data register(1) (r/w): Data byte LSB
SPI_DATA_CSEN	SPI data register(3) (-/w): Chip select enable (command-mode only)
SPI_DATA_CMD	SPI data register(31) (-/w): Command (=1) / data (=0) select

Function Documentation

neorv32_spi_available()

int neorv32_spi_available

(

void

)

Check if SPI unit was synthesized.

Returns

0 if SPI was not synthesized, non-zero if SPI is available.

neorv32_spi_busy()

int neorv32_spi_busy

(

void

)

Check if SPI transceiver is busy or TX FIFO not empty.

Returns

0 if idle, 1 if busy

neorv32_spi_check_cs()

int neorv32_spi_check_cs

(

void

)

Check if any chip-select line is active.

Returns

0 if no CS lines are active, 1 if at least one CS line is active.

neorv32_spi_cs_dis()

void neorv32_spi_cs_dis

(

void

)

Deactivate currently active SPI chip select signal.

Note

The SPI chip select output lines are HIGH when deactivated.

This function is blocking.

neorv32_spi_cs_dis_nonblocking()

void neorv32_spi_cs_dis_nonblocking

(

void

)

Deactivate currently active SPI chip select signal (non-blocking).

Note

The SPI chip select output lines are HIGH when deactivated.

neorv32_spi_cs_en()

void neorv32_spi_cs_en

(

int

cs

)

Activate single SPI chip select signal.

Note

The SPI chip select output lines are LOW when activated.

This function is blocking.

Parameters

cs	Chip select line to activate (0..7).

neorv32_spi_cs_en_nonblocking()

void neorv32_spi_cs_en_nonblocking

(

int

cs

)

Activate single SPI chip select signal (non-blocking).

Note

The SPI chip select output lines are LOW when activated.

Parameters

cs	Chip select line to activate (0..7).

neorv32_spi_disable()

void neorv32_spi_disable

(

void

)

Disable SPI controller.

neorv32_spi_enable()

void neorv32_spi_enable

(

void

)

Enable SPI controller.

neorv32_spi_get_clock_speed()

uint32_t neorv32_spi_get_clock_speed

(

void

)

Get configured clock speed in Hz.

Returns

Actual configured SPI clock speed in Hz.

neorv32_spi_get_fifo_depth()

int neorv32_spi_get_fifo_depth

(

void

)

Get SPI FIFO depth.

Returns

FIFO depth (number of entries), zero if no FIFO implemented

neorv32_spi_get_nonblocking()

uint8_t neorv32_spi_get_nonblocking

(

void

)

Get SPI RX data (non-blocking).

Returns

Receive data (8-bit, LSB-aligned).

neorv32_spi_highspeed_disable()

void neorv32_spi_highspeed_disable

(

void

)

Disable high-speed mode.

neorv32_spi_highspeed_enable()

void neorv32_spi_highspeed_enable

(

void

)

Enable high-speed mode.

neorv32_spi_put_nonblocking()

void neorv32_spi_put_nonblocking

(

uint8_t

tx_data

)

Put SPI TX data (non-blocking).

Parameters

tx_data

Transmit data (8-bit, LSB-aligned).

neorv32_spi_setup()

void neorv32_spi_setup	(	int	prsc,
		int	cdiv,
		int	clk_phase,
		int	clk_polarity,
		uint32_t	irq_mask )

Enable and configure SPI controller. The SPI control register bits are listed in NEORV32_SPI_CTRL_enum.

Parameters

[in]	prsc	Clock prescaler select (0..7). See NEORV32_CLOCK_PRSC_enum. @prama[in] cdiv Clock divider (0..15).
[in]	clk_phase	Clock phase (0=sample on rising edge, 1=sample on falling edge).
[in]	clk_polarity	Clock polarity (when idle).
[in]	irq_mask	Interrupt configuration bit mask (CTRL's irq_* bits).

neorv32_spi_transfer()

uint8_t neorv32_spi_transfer

(

uint8_t

tx_data

)

Perform a single SPI data transfer.

Note

This function is blocking.

Parameters

tx_data

Transmit data (8-bit, LSB-aligned).

Returns

Receive data (8-bit, LSB-aligned).