neorv32_spi.h

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// #################################################################################################
// # << NEORV32: neorv32_spi.h - Serial Peripheral Interface Controller (SPI) HW Driver >>         #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2024, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
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// #    conditions and the following disclaimer.                                                   #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************/
#ifndef neorv32_spi_h
#define neorv32_spi_h
 
/**********************************************************************/
typedef volatile struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;  
  uint32_t DATA;  
} neorv32_spi_t;
 
#define NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE))
 
enum NEORV32_SPI_CTRL_enum {
  SPI_CTRL_EN           =  0, 
  SPI_CTRL_CPHA         =  1, 
  SPI_CTRL_CPOL         =  2, 
  SPI_CTRL_CS_SEL0      =  3, 
  SPI_CTRL_CS_SEL1      =  4, 
  SPI_CTRL_CS_SEL2      =  5, 
  SPI_CTRL_CS_EN        =  6, 
  SPI_CTRL_PRSC0        =  7, 
  SPI_CTRL_PRSC1        =  8, 
  SPI_CTRL_PRSC2        =  9, 
  SPI_CTRL_CDIV0        = 10, 
  SPI_CTRL_CDIV1        = 11, 
  SPI_CTRL_CDIV2        = 12, 
  SPI_CTRL_CDIV3        = 13, 
  SPI_CTRL_HIGHSPEED    = 14, 
  SPI_CTRL_RX_AVAIL     = 16, 
  SPI_CTRL_TX_EMPTY     = 17, 
  SPI_CTRL_TX_NHALF     = 18, 
  SPI_CTRL_TX_FULL      = 19, 
  SPI_CTRL_IRQ_RX_AVAIL = 20, 
  SPI_CTRL_IRQ_TX_EMPTY = 21, 
  SPI_CTRL_IRQ_TX_HALF  = 22, 
  SPI_CTRL_IRQ_IDLE     = 23, 
  SPI_CTRL_FIFO_LSB     = 24, 
  SPI_CTRL_FIFO_MSB     = 27, 
  SPI_CTRL_BUSY         = 31  
};
/**********************************************************************/
int      neorv32_spi_available(void);
void     neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t irq_mask);
void     neorv32_spi_highspeed_enable(void);
void     neorv32_spi_highspeed_disable(void);
uint32_t neorv32_spi_get_clock_speed(void);
void     neorv32_spi_disable(void);
void     neorv32_spi_enable(void);
int      neorv32_spi_get_fifo_depth(void);
void     neorv32_spi_cs_en(int cs);
void     neorv32_spi_cs_dis(void);
uint8_t  neorv32_spi_trans(uint8_t tx_data);
void     neorv32_spi_put_nonblocking(uint8_t tx_data);
uint8_t  neorv32_spi_get_nonblocking(void);
int      neorv32_spi_busy(void);
#endif // neorv32_spi_h