neorv32_twi.h File Reference

Two-Wire Interface Controller (TWI) HW driver header file. More...

#include <stdint.h>

Go to the source code of this file.

Data Structures
struct	neorv32_twi_t

Macros
TWI commands
#define	TWI_CMD_NOP   (0b00)
#define	TWI_CMD_START   (0b01)
#define	TWI_CMD_STOP   (0b10)
#define	TWI_CMD_RTX   (0b11)

Functions
Prototypes
int	neorv32_twi_available (void)
void	neorv32_twi_setup (int prsc, int cdiv, int clkstr)
int	neorv32_twi_get_fifo_depth (void)
void	neorv32_twi_disable (void)
void	neorv32_twi_enable (void)
int	neorv32_twi_sense_scl (void)
int	neorv32_twi_sense_sda (void)
int	neorv32_twi_busy (void)
int	neorv32_twi_get (uint8_t *data)
int	neorv32_twi_trans (uint8_t *data, int mack)
void	neorv32_twi_generate_stop (void)
void	neorv32_twi_generate_start (void)
void	neorv32_twi_send_nonblocking (uint8_t data, int mack)
void	neorv32_twi_generate_stop_nonblocking (void)
void	neorv32_twi_generate_start_nonblocking (void)

IO Device: Two-Wire Interface Controller (TWI)
#define	NEORV32_TWI   ((neorv32_twi_t*) (NEORV32_TWI_BASE))
enum	NEORV32_TWI_CTRL_enum {   TWI_CTRL_EN = 0 , TWI_CTRL_PRSC0 = 1 , TWI_CTRL_PRSC1 = 2 , TWI_CTRL_PRSC2 = 3 ,   TWI_CTRL_CDIV0 = 4 , TWI_CTRL_CDIV1 = 5 , TWI_CTRL_CDIV2 = 6 , TWI_CTRL_CDIV3 = 7 ,   TWI_CTRL_CLKSTR = 8 , TWI_CTRL_FIFO_LSB = 15 , TWI_CTRL_FIFO_MSB = 18 , TWI_CTRL_SENSE_SCL = 27 ,   TWI_CTRL_SENSE_SDA = 28 , TWI_CTRL_TX_FULL = 29 , TWI_CTRL_RX_AVAIL = 30 , TWI_CTRL_BUSY = 31 }
enum	NEORV32_TWI_DCMD_enum {   TWI_DCMD_LSB = 0 , TWI_DCMD_MSB = 7 , TWI_DCMD_ACK = 8 , TWI_DCMD_CMD_LO = 9 ,   TWI_DCMD_CMD_HI = 10 }

Detailed Description

Two-Wire Interface Controller (TWI) HW driver header file.

Note

These functions should only be used if the TWI unit was synthesized (IO_TWI_EN = true).

See also

https://stnolting.github.io/neorv32/sw/files.html

Macro Definition Documentation

NEORV32_TWI

#define NEORV32_TWI   ((neorv32_twi_t*) (NEORV32_TWI_BASE))

TWI module hardware access (neorv32_twi_t)

Enumeration Type Documentation

NEORV32_TWI_CTRL_enum

enum NEORV32_TWI_CTRL_enum

TWI control register bits

Enumerator
TWI_CTRL_EN	TWI control register(0) (r/w): TWI enable
TWI_CTRL_PRSC0	TWI control register(1) (r/w): Clock prescaler select bit 0
TWI_CTRL_PRSC1	TWI control register(2) (r/w): Clock prescaler select bit 1
TWI_CTRL_PRSC2	TWI control register(3) (r/w): Clock prescaler select bit 2
TWI_CTRL_CDIV0	TWI control register(4) (r/w): Clock divider bit 0
TWI_CTRL_CDIV1	TWI control register(5) (r/w): Clock divider bit 1
TWI_CTRL_CDIV2	TWI control register(6) (r/w): Clock divider bit 2
TWI_CTRL_CDIV3	TWI control register(7) (r/w): Clock divider bit 3
TWI_CTRL_CLKSTR	TWI control register(8) (r/w): Enable/allow clock stretching
TWI_CTRL_FIFO_LSB	TWI control register(15) (r/-): log2(FIFO size), lsb
TWI_CTRL_FIFO_MSB	TWI control register(18) (r/-): log2(FIFO size), msb
TWI_CTRL_SENSE_SCL	TWI control register(27) (r/-): current state of the SCL bus line
TWI_CTRL_SENSE_SDA	TWI control register(28) (r/-): current state of the SDA bus line
TWI_CTRL_TX_FULL	TWI control register(29) (r/-): TX FIFO full
TWI_CTRL_RX_AVAIL	TWI control register(30) (r/-): RX FIFO data available
TWI_CTRL_BUSY	TWI control register(31) (r/-): Bus engine busy or TX FIFO not empty

NEORV32_TWI_DCMD_enum

enum NEORV32_TWI_DCMD_enum

TWI command/data register bits

Enumerator
TWI_DCMD_LSB	TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB
TWI_DCMD_MSB	TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB
TWI_DCMD_ACK	TWI data register(8) (r/w): RX = ACK/NACK, TX = MACK
TWI_DCMD_CMD_LO	TWI data register(9) (r/w): CMD lsb
TWI_DCMD_CMD_HI	TWI data register(10) (r/w): CMD msb

Function Documentation

neorv32_twi_available()

int neorv32_twi_available

(

void

)

Check if TWI unit was synthesized.

Returns

0 if TWI was not synthesized, 1 if TWI is available.

neorv32_twi_busy()

int neorv32_twi_busy

(

void

)

Check if TWI controller is busy (TWI bus engine busy or TX FIFO not empty).

Returns

0 if idle, 1 if busy

neorv32_twi_disable()

void neorv32_twi_disable

(

void

)

Disable TWI controller.

neorv32_twi_enable()

void neorv32_twi_enable

(

void

)

Enable TWI controller.

neorv32_twi_generate_start()

void neorv32_twi_generate_start

(

void

)

Generate START (or REPEATED-START) condition.

Note

Blocking function.

neorv32_twi_generate_start_nonblocking()

void neorv32_twi_generate_start_nonblocking

(

void

)

Generate START (or REPEATED-START) condition.

Note

Non-blocking function; does not check the TX FIFO.

neorv32_twi_generate_stop()

void neorv32_twi_generate_stop

(

void

)

Generate STOP condition.

Note

Blocking function.

neorv32_twi_generate_stop_nonblocking()

void neorv32_twi_generate_stop_nonblocking

(

void

)

Generate STOP condition.

Note

Non-blocking function; does not check the TX FIFO.

neorv32_twi_get()

int neorv32_twi_get

(

uint8_t *

data

)

Get received data + ACK/NACH from RX FIFO.

Parameters

[in,out]

data

Pointer for returned data (uint8_t).

Returns

RX FIFO access status (-1 = no data available, 0 = ACK received, 1 = NACK received).

neorv32_twi_get_fifo_depth()

int neorv32_twi_get_fifo_depth

(

void

)

Get TWI FIFO depth.

Returns

FIFO depth (number of entries), zero if no FIFO implemented

neorv32_twi_send_nonblocking()

void neorv32_twi_send_nonblocking	(	uint8_t	data,
		int	mack )

Send data byte (RX can be read via neorv32_twi_get()).

Note

Non-blocking function; does not check the TX FIFO.

Parameters

[in]	data	Data byte to be send.
[in]	mack	Generate ACK by host controller when set.

neorv32_twi_sense_scl()

int neorv32_twi_sense_scl

(

void

)

Get current state of SCL bus line.

Returns

1 if SCL is high, 0 if SCL is low.

neorv32_twi_sense_sda()

int neorv32_twi_sense_sda

(

void

)

Get current state of SDA bus line.

Returns

1 if SDA is high, 0 if SDA is low.

neorv32_twi_setup()

void neorv32_twi_setup	(	int	prsc,
		int	cdiv,
		int	clkstr )

Enable and configure TWI controller. The TWI control register bits are listed in NEORV32_TWI_CTRL_enum.

Parameters

[in]	prsc	Clock prescaler select (0..7). See NEORV32_CLOCK_PRSC_enum.
[in]	cdiv	Clock divider (0..15).
[in]	clkstr	Enable (allow) clock stretching.

neorv32_twi_trans()

int neorv32_twi_trans	(	uint8_t *	data,
		int	mack )

TWI transfer: send data byte and also receive data byte.

Note

Blocking function.

Parameters

[in,out]	data	Pointer for TX/RX data (uint8_t).
[in]	mack	Generate ACK by host controller when set.

Returns

0: ACK received, 1: NACK received.