Enumerator |
---|
UART_CTRL_EN | UART control register(0) (r/w): UART global enable
|
UART_CTRL_SIM_MODE | UART control register(1) (r/w): Simulation output override enable
|
UART_CTRL_HWFC_EN | UART control register(2) (r/w): Enable RTS/CTS hardware flow-control
|
UART_CTRL_PRSC0 | UART control register(3) (r/w): clock prescaler select bit 0
|
UART_CTRL_PRSC1 | UART control register(4) (r/w): clock prescaler select bit 1
|
UART_CTRL_PRSC2 | UART control register(5) (r/w): clock prescaler select bit 2
|
UART_CTRL_BAUD0 | UART control register(6) (r/w): BAUD rate divisor, bit 0
|
UART_CTRL_BAUD1 | UART control register(7) (r/w): BAUD rate divisor, bit 1
|
UART_CTRL_BAUD2 | UART control register(8) (r/w): BAUD rate divisor, bit 2
|
UART_CTRL_BAUD3 | UART control register(9) (r/w): BAUD rate divisor, bit 3
|
UART_CTRL_BAUD4 | UART control register(10) (r/w): BAUD rate divisor, bit 4
|
UART_CTRL_BAUD5 | UART control register(11) (r/w): BAUD rate divisor, bit 5
|
UART_CTRL_BAUD6 | UART control register(12) (r/w): BAUD rate divisor, bit 6
|
UART_CTRL_BAUD7 | UART control register(13) (r/w): BAUD rate divisor, bit 7
|
UART_CTRL_BAUD8 | UART control register(14) (r/w): BAUD rate divisor, bit 8
|
UART_CTRL_BAUD9 | UART control register(15) (r/w): BAUD rate divisor, bit 9
|
UART_CTRL_RX_NEMPTY | UART control register(16) (r/-): RX FIFO not empty
|
UART_CTRL_RX_HALF | UART control register(17) (r/-): RX FIFO at least half-full
|
UART_CTRL_RX_FULL | UART control register(18) (r/-): RX FIFO full
|
UART_CTRL_TX_EMPTY | UART control register(19) (r/-): TX FIFO empty
|
UART_CTRL_TX_NHALF | UART control register(20) (r/-): TX FIFO not at least half-full
|
UART_CTRL_TX_FULL | UART control register(21) (r/-): TX FIFO full
|
UART_CTRL_IRQ_RX_NEMPTY | UART control register(22) (r/w): Fire IRQ if RX FIFO not empty
|
UART_CTRL_IRQ_RX_HALF | UART control register(23) (r/w): Fire IRQ if RX FIFO at least half-full
|
UART_CTRL_IRQ_RX_FULL | UART control register(24) (r/w): Fire IRQ if RX FIFO full
|
UART_CTRL_IRQ_TX_EMPTY | UART control register(25) (r/w): Fire IRQ if TX FIFO empty
|
UART_CTRL_IRQ_TX_NHALF | UART control register(26) (r/w): Fire IRQ if TX FIFO not at least half-full
|
UART_CTRL_RX_OVER | UART control register(30) (r/-): RX FIFO overflow
|
UART_CTRL_TX_BUSY | UART control register(31) (r/-): Transmitter busy or TX FIFO not empty
|