neorv32_dma.h File Reference

Direct Memory Access Controller (DMA) HW driver header file. More...

#include <stdint.h>

Go to the source code of this file.

Data Structures
struct	neorv32_dma_t
struct	neorv32_dma_desc_t

Macros
#define	DMA_CMD_B2B   (0b00 << DMA_TTYPE_QSEL_LSB)
#define	DMA_CMD_B2UW   (0b01 << DMA_TTYPE_QSEL_LSB)
#define	DMA_CMD_B2SW   (0b10 << DMA_TTYPE_QSEL_LSB)
#define	DMA_CMD_W2W   (0b11 << DMA_TTYPE_QSEL_LSB)
#define	DMA_CMD_SRC_CONST   (0b0 << DMA_TTYPE_SRC_INC)
#define	DMA_CMD_SRC_INC   (0b1 << DMA_TTYPE_SRC_INC)
#define	DMA_CMD_DST_CONST   (0b0 << DMA_TTYPE_DST_INC)
#define	DMA_CMD_DST_INC   (0b1 << DMA_TTYPE_DST_INC)
#define	DMA_CMD_ENDIAN   (0b1 << DMA_TTYPE_ENDIAN)

Enumerations
enum	NEORV32_DMA_STATUS_enum {   DMA_STATUS_ERR_WR = -2 , DMA_STATUS_ERR_RD = -1 , DMA_STATUS_IDLE = 0 , DMA_STATUS_BUSY = 1 ,   DMA_STATUS_DONE = 2 }

Functions
Prototypes
int	neorv32_dma_available (void)
void	neorv32_dma_enable (void)
void	neorv32_dma_disable (void)
void	neorv32_dma_transfer (neorv32_dma_desc_t *desc)
int	neorv32_dma_status (void)

IO Device: Direct Memory Access Controller (DMA)
#define	NEORV32_DMA   ((neorv32_dma_t*) (NEORV32_DMA_BASE))
enum	NEORV32_DMA_CTRL_enum {   DMA_CTRL_EN = 0 , DMA_CTRL_START = 1 , DMA_CTRL_ERROR_RD = 28 , DMA_CTRL_ERROR_WR = 29 ,   DMA_CTRL_DONE = 30 , DMA_CTRL_BUSY = 31 }
enum	NEORV32_DMA_TTYPE_enum {   DMA_TTYPE_NUM_LSB = 0 , DMA_TTYPE_NUM_MSB = 23 , DMA_TTYPE_QSEL_LSB = 27 , DMA_TTYPE_QSEL_MSB = 28 ,   DMA_TTYPE_SRC_INC = 29 , DMA_TTYPE_DST_INC = 30 , DMA_TTYPE_ENDIAN = 31 }

Detailed Description

Direct Memory Access Controller (DMA) HW driver header file.

Macro Definition Documentation

DMA_CMD_B2B

#define DMA_CMD_B2B   (0b00 << DMA_TTYPE_QSEL_LSB)

DMA transfer type commands

DMA_CMD_B2SW

#define DMA_CMD_B2SW   (0b10 << DMA_TTYPE_QSEL_LSB)

DMA transfer type commands

DMA_CMD_B2UW

#define DMA_CMD_B2UW   (0b01 << DMA_TTYPE_QSEL_LSB)

DMA transfer type commands

DMA_CMD_DST_CONST

#define DMA_CMD_DST_CONST   (0b0 << DMA_TTYPE_DST_INC)

DMA transfer type commands

DMA_CMD_DST_INC

#define DMA_CMD_DST_INC   (0b1 << DMA_TTYPE_DST_INC)

DMA transfer type commands

DMA_CMD_ENDIAN

#define DMA_CMD_ENDIAN   (0b1 << DMA_TTYPE_ENDIAN)

DMA transfer type commands

DMA_CMD_SRC_CONST

#define DMA_CMD_SRC_CONST   (0b0 << DMA_TTYPE_SRC_INC)

DMA transfer type commands

DMA_CMD_SRC_INC

#define DMA_CMD_SRC_INC   (0b1 << DMA_TTYPE_SRC_INC)

DMA transfer type commands

DMA_CMD_W2W

#define DMA_CMD_W2W   (0b11 << DMA_TTYPE_QSEL_LSB)

DMA transfer type commands

NEORV32_DMA

#define NEORV32_DMA   ((neorv32_dma_t*) (NEORV32_DMA_BASE))

DMA module hardware access (neorv32_dma_t)

Enumeration Type Documentation

NEORV32_DMA_CTRL_enum

enum NEORV32_DMA_CTRL_enum

DMA control and status register bits

Enumerator
DMA_CTRL_EN	DMA control register(0) (r/w): DMA enable
DMA_CTRL_START	DMA control register(1) (-/s): Start configured DMA transfer
DMA_CTRL_ERROR_RD	DMA control register(28) (r/-): Error during read access; SRC_BASE shows the faulting address
DMA_CTRL_ERROR_WR	DMA control register(29) (r/-): Error during write access; DST_BASE shows the faulting address
DMA_CTRL_DONE	DMA control register(30) (r/c): A transfer has been executed when set
DMA_CTRL_BUSY	DMA control register(32) (r/-): DMA busy / transfer in progress

NEORV32_DMA_STATUS_enum

enum NEORV32_DMA_STATUS_enum

DMA status

Enumerator
DMA_STATUS_ERR_WR	write access error during last transfer (-2)
DMA_STATUS_ERR_RD	read access error during last transfer (-1)
DMA_STATUS_IDLE	DMA idle (0)
DMA_STATUS_BUSY	DMA busy (1)
DMA_STATUS_DONE	transfer done (2)

NEORV32_DMA_TTYPE_enum

enum NEORV32_DMA_TTYPE_enum

DMA transfer type bits

Enumerator
DMA_TTYPE_NUM_LSB	DMA transfer type register(0) (r/w): Number of elements to transfer, LSB
DMA_TTYPE_NUM_MSB	DMA transfer type register(23) (r/w): Number of elements to transfer, MSB
DMA_TTYPE_QSEL_LSB	DMA transfer type register(27) (r/w): Data quantity select, LSB
DMA_TTYPE_QSEL_MSB	DMA transfer type register(28) (r/w): Data quantity select, MSB
DMA_TTYPE_SRC_INC	DMA transfer type register(29) (r/w): SRC constant (0) or incrementing (1) address
DMA_TTYPE_DST_INC	DMA transfer type register(30) (r/w): SRC constant (0) or incrementing (1) address
DMA_TTYPE_ENDIAN	DMA transfer type register(31) (r/w): Convert Endianness when set

Function Documentation

neorv32_dma_available()

int neorv32_dma_available

(

void

)

Check if DMA controller was synthesized.

Returns

0 if DMA was not synthesized, 1 if DMA is available.

neorv32_dma_disable()

void neorv32_dma_disable

(

void

)

Disable DMA. This will reset the DMA and will also terminate the current transfer.

neorv32_dma_enable()

void neorv32_dma_enable

(

void

)

Enable DMA.

neorv32_dma_status()

int neorv32_dma_status

(

void

)

Get DMA status.

Returns

Current DMA status (NEORV32_DMA_STATUS_enum)

neorv32_dma_transfer()

void neorv32_dma_transfer

(

neorv32_dma_desc_t *

desc

)

Trigger manual DMA transfer.

Parameters

[in]	base_src	Source base address (has to be aligned to source data type!).
[in]	base_dst	Destination base address (has to be aligned to destination data type!).
[in]	num	Number of elements to transfer (24-bit).
[in]	config	Transfer type configuration/commands.