neorv32_dma.h File Reference

Direct Memory Access Controller (DMA) HW driver header file. More...

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Data Structures
struct	neorv32_dma_t

Macros
#define	DMA_CMD_B2B   (0b00 << DMA_TTYPE_QSEL_LSB)
#define	DMA_CMD_B2UW   (0b01 << DMA_TTYPE_QSEL_LSB)
#define	DMA_CMD_B2SW   (0b10 << DMA_TTYPE_QSEL_LSB)
#define	DMA_CMD_W2W   (0b11 << DMA_TTYPE_QSEL_LSB)
#define	DMA_CMD_SRC_CONST   (0b0 << DMA_TTYPE_SRC_INC)
#define	DMA_CMD_SRC_INC   (0b1 << DMA_TTYPE_SRC_INC)
#define	DMA_CMD_DST_CONST   (0b0 << DMA_TTYPE_DST_INC)
#define	DMA_CMD_DST_INC   (0b1 << DMA_TTYPE_DST_INC)
#define	DMA_CMD_ENDIAN   (0b1 << DMA_TTYPE_ENDIAN)

Enumerations
enum	NEORV32_DMA_STATUS_enum { DMA_STATUS_ERR_WR = -2 , DMA_STATUS_ERR_RD = -1 , DMA_STATUS_IDLE = 0 , DMA_STATUS_BUSY = 1 }

Functions
Prototypes
int	neorv32_dma_available (void)
void	neorv32_dma_enable (void)
void	neorv32_dma_disable (void)
void	neorv32_dma_fence_enable (void)
void	neorv32_dma_fence_disable (void)
void	neorv32_dma_transfer (uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config)
void	neorv32_dma_transfer_auto (uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config, int firq_sel)
int	neorv32_dma_status (void)
int	neorv32_dma_done (void)

IO Device: Direct Memory Access Controller (DMA)
#define	NEORV32_DMA   ((neorv32_dma_t*) (NEORV32_DMA_BASE))
enum	NEORV32_DMA_CTRL_enum {   DMA_CTRL_EN = 0 , DMA_CTRL_AUTO = 1 , DMA_CTRL_FENCE = 2 , DMA_CTRL_ERROR_RD = 8 ,   DMA_CTRL_ERROR_WR = 9 , DMA_CTRL_BUSY = 10 , DMA_CTRL_DONE = 11 , DMA_CTRL_FIRQ_SEL_LSB = 16 ,   DMA_CTRL_FIRQ_SEL_MSB = 19 }
enum	NEORV32_DMA_TTYPE_enum {   DMA_TTYPE_NUM_LSB = 0 , DMA_TTYPE_NUM_MSB = 23 , DMA_TTYPE_QSEL_LSB = 27 , DMA_TTYPE_QSEL_MSB = 28 ,   DMA_TTYPE_SRC_INC = 29 , DMA_TTYPE_DST_INC = 30 , DMA_TTYPE_ENDIAN = 31 }

Detailed Description

Direct Memory Access Controller (DMA) HW driver header file.

Note

These functions should only be used if the DMA controller was synthesized (IO_DMA_EN = true).

Macro Definition Documentation

DMA_CMD_B2B

#define DMA_CMD_B2B   (0b00 << DMA_TTYPE_QSEL_LSB)

DMA transfer type commands

DMA_CMD_B2SW

#define DMA_CMD_B2SW   (0b10 << DMA_TTYPE_QSEL_LSB)

DMA transfer type commands

DMA_CMD_B2UW

#define DMA_CMD_B2UW   (0b01 << DMA_TTYPE_QSEL_LSB)

DMA transfer type commands

DMA_CMD_DST_CONST

#define DMA_CMD_DST_CONST   (0b0 << DMA_TTYPE_DST_INC)

DMA transfer type commands

DMA_CMD_DST_INC

#define DMA_CMD_DST_INC   (0b1 << DMA_TTYPE_DST_INC)

DMA transfer type commands

DMA_CMD_ENDIAN

#define DMA_CMD_ENDIAN   (0b1 << DMA_TTYPE_ENDIAN)

DMA transfer type commands

DMA_CMD_SRC_CONST

#define DMA_CMD_SRC_CONST   (0b0 << DMA_TTYPE_SRC_INC)

DMA transfer type commands

DMA_CMD_SRC_INC

#define DMA_CMD_SRC_INC   (0b1 << DMA_TTYPE_SRC_INC)

DMA transfer type commands

DMA_CMD_W2W

#define DMA_CMD_W2W   (0b11 << DMA_TTYPE_QSEL_LSB)

DMA transfer type commands

NEORV32_DMA

#define NEORV32_DMA   ((neorv32_dma_t*) (NEORV32_DMA_BASE))

DMA module hardware access (neorv32_dma_t)

Enumeration Type Documentation

NEORV32_DMA_CTRL_enum

enum NEORV32_DMA_CTRL_enum

DMA control and status register bits

Enumerator
DMA_CTRL_EN	DMA control register(0) (r/w): DMA enable
DMA_CTRL_AUTO	DMA control register(1) (r/w): Automatic trigger mode enable
DMA_CTRL_FENCE	DMA control register(2) (r/w): Issue FENCE downstream operation when DMA transfer is completed
DMA_CTRL_ERROR_RD	DMA control register(8) (r/-): Error during read access; SRC_BASE shows the faulting address
DMA_CTRL_ERROR_WR	DMA control register(9) (r/-): Error during write access; DST_BASE shows the faulting address
DMA_CTRL_BUSY	DMA control register(10) (r/-): DMA busy / transfer in progress
DMA_CTRL_DONE	DMA control register(11) (r/c): A transfer was executed when set
DMA_CTRL_FIRQ_SEL_LSB	DMA control register(16) (r/w): FIRQ trigger select LSB
DMA_CTRL_FIRQ_SEL_MSB	DMA control register(19) (r/w): FIRQ trigger select MSB

NEORV32_DMA_STATUS_enum

enum NEORV32_DMA_STATUS_enum

DMA status

Enumerator
DMA_STATUS_ERR_WR	write access error during last transfer (-2)
DMA_STATUS_ERR_RD	read access error during last transfer (-1)
DMA_STATUS_IDLE	DMA idle (0)
DMA_STATUS_BUSY	DMA busy (1)

NEORV32_DMA_TTYPE_enum

enum NEORV32_DMA_TTYPE_enum

DMA transfer type bits

Enumerator
DMA_TTYPE_NUM_LSB	DMA transfer type register(0) (r/w): Number of elements to transfer, LSB
DMA_TTYPE_NUM_MSB	DMA transfer type register(23) (r/w): Number of elements to transfer, MSB
DMA_TTYPE_QSEL_LSB	DMA transfer type register(27) (r/w): Data quantity select, LSB
DMA_TTYPE_QSEL_MSB	DMA transfer type register(28) (r/w): Data quantity select, MSB
DMA_TTYPE_SRC_INC	DMA transfer type register(29) (r/w): SRC constant (0) or incrementing (1) address
DMA_TTYPE_DST_INC	DMA transfer type register(30) (r/w): SRC constant (0) or incrementing (1) address
DMA_TTYPE_ENDIAN	DMA transfer type register(31) (r/w): Convert Endianness when set

Function Documentation

neorv32_dma_available()

int neorv32_dma_available

(

void

)

Check if DMA controller was synthesized.

Returns

0 if DMA was not synthesized, 1 if DMA is available.

neorv32_dma_disable()

void neorv32_dma_disable

(

void

)

Disable DMA. This will reset the DMA and will also terminate the current transfer.

neorv32_dma_done()

int neorv32_dma_done

(

void

)

Check if a transfer has actually been executed.

Returns

0 if no transfer was executed, 1 if a transfer has actually been executed. Use neorv32_dma_status(void) to check if there was an error during that transfer.

neorv32_dma_enable()

void neorv32_dma_enable

(

void

)

Enable DMA.

neorv32_dma_fence_disable()

void neorv32_dma_fence_disable

(

void

)

Disable memory barrier (fence).

neorv32_dma_fence_enable()

void neorv32_dma_fence_enable

(

void

)

Enable memory barrier (fence): issue a FENCE operation when DMA transfer completes without errors.

neorv32_dma_status()

int neorv32_dma_status

(

void

)

Get DMA status.

Returns

Current DMA status (NEORV32_DMA_STATUS_enum)

neorv32_dma_transfer()

void neorv32_dma_transfer	(	uint32_t	base_src,
		uint32_t	base_dst,
		uint32_t	num,
		uint32_t	config )

Trigger manual DMA transfer.

Parameters

[in]	base_src	Source base address (has to be aligned to source data type!).
[in]	base_dst	Destination base address (has to be aligned to destination data type!).
[in]	num	Number of elements to transfer (24-bit).
[in]	config	Transfer type configuration/commands.

neorv32_dma_transfer_auto()

void neorv32_dma_transfer_auto	(	uint32_t	base_src,
		uint32_t	base_dst,
		uint32_t	num,
		uint32_t	config,
		int	firq_sel )

Configure automatic DMA transfer (triggered by CPU FIRQ).

Parameters

[in]	base_src	Source base address (has to be aligned to source data type!).
[in]	base_dst	Destination base address (has to be aligned to destination data type!).
[in]	num	Number of elements to transfer (24-bit).
[in]	config	Transfer type configuration/commands.
[in]	firq_sel	FIRQ trigger select (NEORV32_CSR_MIP_enum); only FIRQ0..FIRQ15 = 16..31.