neorv32_dma.h File Reference

Direct Memory Access Controller (DMA) HW driver header file. More...

#include <stdint.h>

Go to the source code of this file.

Data Structures
struct	neorv32_dma_t

Enumerations
enum	NEORV32_DMA_STATUS_enum { DMA_STATUS_ERROR = -1 , DMA_STATUS_IDLE = 0 , DMA_STATUS_BUSY = 1 , DMA_STATUS_DONE = 2 }

Functions
Prototypes
int	neorv32_dma_available (void)
int	neorv32_dma_get_descriptor_fifo_depth (void)
int	neorv32_dma_descriptor_fifo_full (void)
int	neorv32_dma_descriptor_fifo_empty (void)
void	neorv32_dma_enable (void)
void	neorv32_dma_disable (void)
void	neorv32_dma_irq_ack (void)
int	neorv32_dma_program (uint32_t src_addr, uint32_t dst_addr, uint32_t config)
void	neorv32_dma_program_nocheck (uint32_t src_addr, uint32_t dst_addr, uint32_t config)
void	neorv32_dma_start (void)
int	neorv32_dma_status (void)

IO Device: Direct Memory Access Controller (DMA)
#define	NEORV32_DMA   ((neorv32_dma_t*) (NEORV32_DMA_BASE))
enum	NEORV32_DMA_CTRL_enum {   DMA_CTRL_EN = 0 , DMA_CTRL_START = 1 , DMA_CTRL_DFIFO_LSB = 16 , DMA_CTRL_DFIFO_MSB = 19 ,   DMA_CTRL_ACK = 26 , DMA_CTRL_DEMPTY = 27 , DMA_CTRL_DFULL = 28 , DMA_CTRL_ERROR = 29 ,   DMA_CTRL_DONE = 30 , DMA_CTRL_BUSY = 31 }
enum	NEORV32_DMA_CONF_enum {   DMA_CONF_NUM_LSB = 0 , DMA_CONF_NUM_MSB = 23 , DMA_CONF_BSWAP = 27 , DMA_CONF_SRC_LSB = 28 ,   DMA_CONF_SRC_MSB = 29 , DMA_CONF_DST_LSB = 30 , DMA_CONF_DST_MSB = 31 }
#define	DMA_SRC_CONST_BYTE   (DMA_TYPE_CONST_BYTE << DMA_CONF_SRC_LSB)
#define	DMA_SRC_CONST_WORD   (DMA_TYPE_CONST_WORD << DMA_CONF_SRC_LSB)
#define	DMA_SRC_INC_BYTE   (DMA_TYPE_INC_BYTE << DMA_CONF_SRC_LSB)
#define	DMA_SRC_INC_WORD   (DMA_TYPE_INC_WORD << DMA_CONF_SRC_LSB)
#define	DMA_DST_CONST_BYTE   (DMA_TYPE_CONST_BYTE << DMA_CONF_DST_LSB)
#define	DMA_DST_CONST_WORD   (DMA_TYPE_CONST_WORD << DMA_CONF_DST_LSB)
#define	DMA_DST_INC_BYTE   (DMA_TYPE_INC_BYTE << DMA_CONF_DST_LSB)
#define	DMA_DST_INC_WORD   (DMA_TYPE_INC_WORD << DMA_CONF_DST_LSB)
#define	DMA_BSWAP   (1 << DMA_CONF_BSWAP)
enum	NEORV32_DMA_TYPE_enum { DMA_TYPE_CONST_BYTE = 0b00 , DMA_TYPE_CONST_WORD = 0b01 , DMA_TYPE_INC_BYTE = 0b10 , DMA_TYPE_INC_WORD = 0b11 }

Detailed Description

Direct Memory Access Controller (DMA) HW driver header file.

Macro Definition Documentation

DMA_BSWAP

#define DMA_BSWAP   (1 << DMA_CONF_BSWAP)

Endianness conversion

DMA_DST_CONST_BYTE

#define DMA_DST_CONST_BYTE   (DMA_TYPE_CONST_BYTE << DMA_CONF_DST_LSB)

destination aliases

DMA_DST_CONST_WORD

#define DMA_DST_CONST_WORD   (DMA_TYPE_CONST_WORD << DMA_CONF_DST_LSB)

source aliases

DMA_DST_INC_BYTE

#define DMA_DST_INC_BYTE   (DMA_TYPE_INC_BYTE << DMA_CONF_DST_LSB)

source aliases

DMA_DST_INC_WORD

#define DMA_DST_INC_WORD   (DMA_TYPE_INC_WORD << DMA_CONF_DST_LSB)

source aliases

DMA_SRC_CONST_BYTE

#define DMA_SRC_CONST_BYTE   (DMA_TYPE_CONST_BYTE << DMA_CONF_SRC_LSB)

source aliases

DMA_SRC_CONST_WORD

#define DMA_SRC_CONST_WORD   (DMA_TYPE_CONST_WORD << DMA_CONF_SRC_LSB)

source aliases

DMA_SRC_INC_BYTE

#define DMA_SRC_INC_BYTE   (DMA_TYPE_INC_BYTE << DMA_CONF_SRC_LSB)

source aliases

DMA_SRC_INC_WORD

#define DMA_SRC_INC_WORD   (DMA_TYPE_INC_WORD << DMA_CONF_SRC_LSB)

source aliases

NEORV32_DMA

#define NEORV32_DMA   ((neorv32_dma_t*) (NEORV32_DMA_BASE))

DMA module hardware handle (neorv32_dma_t)

Enumeration Type Documentation

NEORV32_DMA_CONF_enum

enum NEORV32_DMA_CONF_enum

DMA transfer configuration

Enumerator
DMA_CONF_NUM_LSB	DMA transfer type register(0) (r/w): Number of elements to transfer, LSB
DMA_CONF_NUM_MSB	DMA transfer type register(23) (r/w): Number of elements to transfer, MSB
DMA_CONF_BSWAP	DMA transfer type register(27) (r/w): Swap byte order when set
DMA_CONF_SRC_LSB	DMA transfer type register(28) (r/w): SRC transfer type select (NEORV32_DMA_TYPE_enum), LSB
DMA_CONF_SRC_MSB	DMA transfer type register(29) (r/w): SRC transfer type select (NEORV32_DMA_TYPE_enum), MSB
DMA_CONF_DST_LSB	DMA transfer type register(30) (r/w): DST transfer type select (NEORV32_DMA_TYPE_enum), LSB
DMA_CONF_DST_MSB	DMA transfer type register(31) (r/w): DST transfer type select (NEORV32_DMA_TYPE_enum), MSB

NEORV32_DMA_CTRL_enum

enum NEORV32_DMA_CTRL_enum

DMA control and status register bits

Enumerator
DMA_CTRL_EN	DMA control register(0) (r/w): DMA enable
DMA_CTRL_START	DMA control register(1) (-/w): Start DMA transfer(s)
DMA_CTRL_DFIFO_LSB	DMA control register(16) (r/-): log2(descriptor FIFO size), LSB
DMA_CTRL_DFIFO_MSB	DMA control register(19) (r/-): log2(descriptor FIFO size), MSB
DMA_CTRL_ACK	DMA control register(26) (-/w): Set to clear ERROR and DONE flags
DMA_CTRL_DEMPTY	DMA control register(27) (r/-): Descriptor FIFO is empty
DMA_CTRL_DFULL	DMA control register(28) (r/-): Descriptor FIFO is full
DMA_CTRL_ERROR	DMA control register(29) (r/-): Bus access error during transfer
DMA_CTRL_DONE	DMA control register(30) (r/-): A transfer has been executed when set
DMA_CTRL_BUSY	DMA control register(32) (r/-): DMA busy / transfer in progress

NEORV32_DMA_STATUS_enum

enum NEORV32_DMA_STATUS_enum

DMA status

Enumerator
DMA_STATUS_ERROR	bus access error during last transfer (-1)
DMA_STATUS_IDLE	DMA idle (0)
DMA_STATUS_BUSY	DMA busy (1)
DMA_STATUS_DONE	transfer done (2)

NEORV32_DMA_TYPE_enum

enum NEORV32_DMA_TYPE_enum

DMA transfer type select / commands

Enumerator
DMA_TYPE_CONST_BYTE	constant byte
DMA_TYPE_CONST_WORD	constant word
DMA_TYPE_INC_BYTE	incrementing byte
DMA_TYPE_INC_WORD	incrementing word

Function Documentation

neorv32_dma_available()

int neorv32_dma_available

(

void

)

Check if DMA controller was synthesized.

Returns

0 if DMA was not synthesized, non-zero if DMA is available.

neorv32_dma_descriptor_fifo_empty()

int neorv32_dma_descriptor_fifo_empty

(

void

)

Check if descriptor FIFO is empty.

Returns

Non-zero if FIFO is empty, zero otherwise.

neorv32_dma_descriptor_fifo_full()

int neorv32_dma_descriptor_fifo_full

(

void

)

Check if descriptor FIFO is full.

Returns

Non-zero if FIFO is full, zero otherwise.

neorv32_dma_disable()

void neorv32_dma_disable

(

void

)

Disable DMA. This will reset the DMA and will also terminate the current transfer.

neorv32_dma_enable()

void neorv32_dma_enable

(

void

)

Enable DMA.

neorv32_dma_get_descriptor_fifo_depth()

int neorv32_dma_get_descriptor_fifo_depth

(

void

)

Get DMA descriptor FIFO depth.

Returns

FIFO depth (number of entries)

neorv32_dma_irq_ack()

void neorv32_dma_irq_ack

(

void

)

Manually clear pending DMA interrupt. This will also clear the transfer-error and transfer-done status flags.

neorv32_dma_program()

int neorv32_dma_program	(	uint32_t	src_addr,
		uint32_t	dst_addr,
		uint32_t	config )

Program DMA descriptor.

Parameters

[in]	base_src	Source data base address.
[in]	base_dst	Destination data base address.
[in]	config	Transfer type configuration (NEORV32_DMA_CONF_enum).

Returns

0 if programming was successful; if the descriptor FIFO does not provide enough space for the entire descriptor, a negative value is returned that represents the number of missing FIFO entries.

neorv32_dma_program_nocheck()

void neorv32_dma_program_nocheck	(	uint32_t	src_addr,
		uint32_t	dst_addr,
		uint32_t	config )

Program DMA descriptor (without checking FIFO level).

Warning

Descriptor FIFO might overflow. Use with care.

Parameters

[in]	base_src	Source data base address.
[in]	base_dst	Destination data base address.
[in]	config	Transfer type configuration (NEORV32_DMA_CONF_enum).

neorv32_dma_start()

void neorv32_dma_start

(

void

)

Trigger pre-programmed DMA transfer(s)

neorv32_dma_status()

int neorv32_dma_status

(

void

)

Get DMA status.

Returns

Current DMA status (NEORV32_DMA_STATUS_enum)