neorv32_dma.h

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// ================================================================================ //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
// Copyright (c) NEORV32 contributors.                                              //
// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  //
// Licensed under the BSD-3-Clause license, see LICENSE for details.                //
// SPDX-License-Identifier: BSD-3-Clause                                            //
// ================================================================================ //
 
#ifndef neorv32_dma_h
#define neorv32_dma_h
 
#include <stdint.h>
 
 
/**********************************************************************/
typedef volatile struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;     
  uint32_t SRC_BASE; 
  uint32_t DST_BASE; 
  uint32_t TTYPE;    
} neorv32_dma_t;
 
#define NEORV32_DMA ((neorv32_dma_t*) (NEORV32_DMA_BASE))
 
enum NEORV32_DMA_CTRL_enum {
  DMA_CTRL_EN           =  0, 
  DMA_CTRL_AUTO         =  1, 
  DMA_CTRL_FENCE        =  2, 
  DMA_CTRL_ERROR_RD     =  8, 
  DMA_CTRL_ERROR_WR     =  9, 
  DMA_CTRL_BUSY         = 10, 
  DMA_CTRL_DONE         = 11, 
  DMA_CTRL_FIRQ_TYPE    = 15, 
  DMA_CTRL_FIRQ_SEL_LSB = 16, 
  DMA_CTRL_FIRQ_SEL_MSB = 19  
};
 
enum NEORV32_DMA_TTYPE_enum {
  DMA_TTYPE_NUM_LSB  =  0, 
  DMA_TTYPE_NUM_MSB  = 23, 
  DMA_TTYPE_QSEL_LSB = 27, 
  DMA_TTYPE_QSEL_MSB = 28, 
  DMA_TTYPE_SRC_INC  = 29, 
  DMA_TTYPE_DST_INC  = 30, 
  DMA_TTYPE_ENDIAN   = 31  
};
/**********************************************************************/
#define DMA_CMD_B2B  (0b00 << DMA_TTYPE_QSEL_LSB) // byte to byte
#define DMA_CMD_B2UW (0b01 << DMA_TTYPE_QSEL_LSB) // byte to unsigned word
#define DMA_CMD_B2SW (0b10 << DMA_TTYPE_QSEL_LSB) // byte to signed word
#define DMA_CMD_W2W  (0b11 << DMA_TTYPE_QSEL_LSB) // word to word
 
#define DMA_CMD_SRC_CONST (0b0 << DMA_TTYPE_SRC_INC) // constant source address
#define DMA_CMD_SRC_INC   (0b1 << DMA_TTYPE_SRC_INC) // incrementing source address
 
#define DMA_CMD_DST_CONST (0b0 << DMA_TTYPE_DST_INC) // constant destination address
#define DMA_CMD_DST_INC   (0b1 << DMA_TTYPE_DST_INC) // incrementing destination address
 
#define DMA_CMD_ENDIAN (0b1 << DMA_TTYPE_ENDIAN) // convert endianness
/**********************************************************************/
enum NEORV32_DMA_STATUS_enum {
  DMA_STATUS_ERR_WR = -2, 
  DMA_STATUS_ERR_RD = -1, 
  DMA_STATUS_IDLE   =  0, 
  DMA_STATUS_BUSY   =  1  
};
 
 
/**********************************************************************/
int  neorv32_dma_available(void);
void neorv32_dma_enable(void);
void neorv32_dma_disable(void);
void neorv32_dma_fence_enable(void);
void neorv32_dma_fence_disable(void);
void neorv32_dma_transfer(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config);
void neorv32_dma_transfer_auto(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config, int firq_sel, int firq_type);
int  neorv32_dma_status(void);
int  neorv32_dma_done(void);
#endif // neorv32_dma_h